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The National Semiconductor 100130DC is a D-type transparent latch belonging to the 100K series. It integrates three independent latching circuits within a single package, providing a 3:3 configuration for data storage applications. The device operates with a supply voltage range of -4.2V to -5.7V, typical for negative logic systems. It features standard output types and is housed in a 24-CDIP package with a width of 0.600 inches (15.24mm). This component is designed for reliable digital signal latching in industrial and commercial environments.
Verify the manufacturer origin, as National Semiconductor assets are now managed by Texas Instruments. Confirm the package type matches the required 24-CDIP footprint. Ensure the supply voltage requirements align with your system's negative rail specifications. Check for date code freshness if long-term reliability is critical. Validate that the 100K series speed grade meets your circuit timing constraints.
Select this component when a triple-channel latch is required within a single integrated circuit. Consider the 100K series propagation delay characteristics against your system clock speeds. Evaluate the need for negative voltage operation versus positive logic alternatives. The CDIP package offers robust mechanical stability for through-hole mounting. Verify compatibility with existing bus architectures requiring transparent latch behavior.
The 100130DC is part of the broader 100K series of high-speed logic components originally developed by National Semiconductor. This series was widely used in computing and telecommunications equipment during the era of bipolar logic dominance. The transition of National Semiconductor to Texas Instruments means datasheets and support may be archived under TI branding. The 100K family is known for its balanced performance between speed and power consumption compared to earlier TTL standards.
Public confirmed substitute part numbers are not available in the provided documentation.