14550R-500

Overview

The Neuron 6050 Processor is an IP processor for IzoT-enabled devices, optimized for smart control networks. It features a user-configurable system clock from 5MHz to 80MHz, utilizing a 10MHz external crystal and internal PLL. The chip integrates 16KB ROM and 64KB RAM (44KB user-accessible), with no on-chip user NVM. It supports up to 254 Network Variables and includes a unique 48-bit IEEE MAC ID. The device provides a 5-pin communications port compatible with various transceivers and offers backward compatibility with LonTalk while supporting native IP addressing.

Feature Summary

• Supports four operating modes: LonTalk, LonTalk/IP, BACnet/IP, and Any IP.
• Integrates three independent processors (MAC, NET, APP) plus an IRQ CPU at higher speeds.
• Features a versatile 5-pin communications port with 3.3V drive and 5V-tolerant inputs.
• Includes hardware multiplication/division and supports up to 254 Network Variable entries.

Applications

• Industrial Internet of Things (IIoT) control devices
• LonTalk/IP or BACnet/IP network nodes
• Smart building automation systems

Part Context

The model 14550R-500 corresponds to the Neuron 6050 Processor, which supports all four specified operating modes. This component is part of Echelon's IzoT Platform, designed to consolidate multiple control protocols and modernize existing LONWORKS devices with IP capabilities.

Replacement Considerations

Transitioning from Neuron 3120/3150 chips requires hardware redesign due to different supply voltages and memory architectures. Designs using Neuron 5000 with external flash may transition with minimal changes. Differential Mode transceivers are not supported; Single-Ended Mode with external conversion circuitry is required.

FAQ

Does the Neuron 6050 support Differential Mode for its communications port?

No, the Neuron 6050 does not support Differential Mode. Devices requiring this must use Single-Ended Mode with external circuitry for conversion.

What is the maximum system clock frequency?

The internal system clock can be configured up to 80MHz using a 10MHz external crystal and an internal PLL.

How is firmware managed given the lack of on-chip NVM?

Firmware is loaded into RAM from off-chip SPI flash memory during reset. Writes to NVM are shadowed in RAM and pushed out by the firmware.