23S09E-1HPGGI

Overview

The Renesas 23S09E-1HPGGI is a high-speed phase-locked loop (PLL) clock buffer designed for zero-delay clock distribution. It accepts one reference input and drives two banks of outputs, specifically configured as five and four low-skew clocks respectively. The device operates within a frequency range of 10MHz to 200MHz and requires a 3V to 3.6V power supply. It features on-chip PLLs that lock to an input clock on the REF pin, with feedback obtained from the CLKOUT pad. In the absence of an input clock, the device enters a low-power down mode with tri-stated outputs.

Feature Summary

• Zero-delay operation aligning incoming and output clock phases
• Operates at frequencies up to 200MHz
• Drives 1:9 output ratio across two separate banks
• Low jitter performance with cycle-to-cycle jitter less than 200ps

Applications

• High-speed clock distribution in digital systems
• Phase-locked loop clock buffering applications
• Systems requiring low-skew clock alignment

Part Context

This component belongs to the 23S09 family of zero-delay buffers. It is a 16-pin version derived from the 23S05 architecture. The -1H suffix indicates a variant with higher drive capability compared to standard -1 devices, supporting operation up to 133MHz or higher depending on specific configuration limits.