2746595

Overview

Phoenix Contact IBS SRE 1A (Order No. 2746595) is a serial register expansion chip designed for the INTERBUS SUPI protocol family. Housed in a QFP44 package, it expands internal data registers by up to six additional words accessible via a microprocessor interface. It operates on a 5V supply (4.5V to 5.5V) within an industrial temperature range of -40°C to +85°C. The chip features an 8-bit bidirectional data bus and a 4-bit address bus for parallel access. Serial communication connects to the IBS SUPI via SDI/SDO pins, while hardware or software configuration sets the data length.

Feature Summary

• Expands INTERBUS slave device data capacity with up to six additional data words
• Provides parallel microprocessor interface for direct register access
• Supports both hardware pin configuration and software register configuration for data length
• Includes interrupt request logic for synchronization with INTERBUS cycles

Applications

• Custom INTERBUS slave device implementation requiring extended I/O data
• Integration with IBS SUPI protocol chips for sensor/actuator networks
• Industrial automation systems needing asynchronous CPU access to bus data

Procurement Notes

Verify the component matches Order Number 2746595 and designation IBS SRE 1A. Confirm the QFP44 housing type and check for ESD handling requirements during installation. Ensure the application design accounts for the 5V DC supply voltage and industrial temperature specifications. Cross-reference with official Phoenix Contact documentation for accurate signal timing and pin assignments.

Selection Notes

Select this chip when the internal registers of the IBS SUPI protocol chip are insufficient for the required I/O data volume. It allows expansion by up to six words. Consider whether hardware wiring or software configuration is preferred for setting the data length. Ensure the microprocessor interface timing meets the specified write and read access constraints for reliable operation.

Part Context

The IBS SRE 1A is part of the INTERBUS SUPI protocol chip family from Phoenix Contact. It serves as an ASIC-based expansion unit for serial sensor/actuator bus systems. Designed in 0.8-µm gate array technology, it complements the main protocol chips by providing additional memory space for process data exchange between the INTERBUS master and slave applications.

Replacement Considerations

No direct public substitute part numbers are documented for this specific register expansion chip. If the IBS SUPI clock source is used, ensure the oscillator circuit supports the required timing. For alternative architectures, consult Phoenix Contact regarding newer INTERBUS-compatible components or different bus technologies.

FAQ

How is the data length of the IBS SRE 1A configured?

The data length can be set via hardware by wiring pins K0, K1, and K2, or via software by writing to the CONFREG configuration register at relative address 12.

What is the purpose of the /IRQ signal?

The /IRQ signal provides an interrupt request to synchronize CPU access with the INTERBUS cycle, preventing inconsistent data transmission during latch phases.

How does the IBS SRE 1A connect to the IBS SUPI?

It connects via serial data inputs/outputs (SDI/SDO) and control signals. SDI connects to ToExR1/ToExR2 of the SUPI, and SDO connects to FromExR to close the data ring.