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74ABT00PW,118
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Product Detailed Parameters
- Description：IC GATE NAND 4CH 2-INP 14TSSOP
- Series：74ABT
- Mfr：Nexperia USA Inc.
- Package：Tape & Reel (TR),Bulk
- Logic Type：NAND Gate
- Number of Circuits：4
- Number of Inputs：2
- Features：-
- Voltage - Supply：4.5V ~ 5.5V
- Current - Quiescent (Max)：50 µA
- Current - Output High, Low：15mA, 20mA
- Input Logic Level - Low：0.8V
- Input Logic Level - High：2V
- Max Propagation Delay @ V, Max CL：3.6ns @ 5V, 50pF
- Operating Temperature：-40°C ~ 85°C
- Mounting Type：Surface Mount
- Supplier Device Package：14-TSSOP
- Package / Case：14-TSSOP (0.173", 4.40mm Width)
- Grade：-
- Qualification：-
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Overview
The Nexperia 74ABT00PW,118 is a quad 2-input NAND gate in a TSSOP14 package. It operates on a supply voltage of 4.5 V to 5.5 V with BiCMOS technology for high speed and output drive. Key electrical parameters include a low-level output current of 20 mA and a high-level output current of -15 mA. Propagation delays range from 1.0 ns to 4.1 ns at 5.0 V. The device supports partial power-down via IOFF circuitry and withstands latch-up currents exceeding 500 mA.
Feature Summary
- BiCMOS technology provides high-speed operation and strong output drive capabilities.
- IOFF circuitry enables partial power-down mode by disabling outputs to prevent backflow current.
- Direct interface compatibility with TTL logic levels simplifies system integration.
- Robust protection features include ESD tolerance exceeding 2000 V (HBM) and latch-up protection over 500 mA.
Applications
- Partial power-down applications requiring controlled output isolation
- Mixed-signal systems interfacing with TTL level standards
- High-speed digital logic processing circuits
Procurement Notes
Verify the specific ordering suffix
Selection Notes
Select this component when designing 5V logic systems requiring fast switching speeds and robust noise immunity. The BiCMOS architecture offers superior drive strength compared to standard CMOS alternatives. Ensure the design accommodates the 4.5 V to 5.5 V supply range and utilizes the IOFF feature if partial power management is required for the target application.
Part Context
This part belongs to the 74ABT series, which utilizes Bipolar-CMOS technology to achieve performance levels between standard 74HC and 74F families. The PW suffix indicates a plastic thin shrink small outline package (TSSOP14), suitable for surface-mount assembly where space efficiency is prioritized alongside high-density circuit board layouts.
Replacement Considerations
Check for 74ABT00D as an alternative SO14 package version from the same manufacturer. Verify pinout compatibility before substituting with other quad NAND gates from different logic families.
FAQ
How does the IOFF circuitry function in this device?
The IOFF circuitry disables the outputs when the device is powered down, preventing potentially damaging backflow current through the device during partial power-down applications.
What is the maximum latch-up protection rating?
The device exceeds 500 mA per JESD78B Class II Level A for latch-up protection.
