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74ACTQ573SCX is listed in the Latches range at ChipApex. The manufacturer field lists onsemi. Its product description is IC D-TYPE TRANSP SGL 8:8 20SOIC. Review the specifications below when checking this part for your BOM.
The onsemi 74ACTQ573SCX is an octal latch with 3-STATE outputs belonging to the ACTQ logic series. It operates within a supply voltage range of 4.5 V to 5.5 V and supports an operating temperature from -40°C to +85°C. The device features eight D-type latches with buffered common Latch Enable (LE) and Output Enable (OE) inputs. Outputs source or sink 24 mA. Propagation delay from data input to output is typically 6.5 ns at 5 V, while the LE-to-output delay is typically 7.0 ns. Quiescent supply current is typically 0.6 mA.
Verify the specific ordering code suffix against the manufacturer's documentation to confirm the package type. The 'SC' designation indicates a 20-Lead Small Outline Integrated Circuit (SOIC). Confirm that the required tape and reel packaging is requested by appending the appropriate suffix letter if applicable. Ensure compatibility with the target system's voltage and temperature specifications before procurement.
Select this component when a high-speed octal latch with 3-STATE outputs is required for systems operating at 5 V. The ACTQ series offers reduced ICC and IOZ compared to standard AC/ACT families. Consider the QSOP package availability if space constraints require a quarter-size outline, though the SC variant provides a standard SOIC footprint. Verify pinout orientation relative to the processor interface requirements.
This part belongs to the 74ACQ/ACTQ family of octal latches. It is functionally identical to the 74ACQ/ACTQ373 but differs in pin configuration, with inputs and outputs positioned on opposite sides of the package. This layout simplifies PCB routing for microprocessor interfaces. The device is manufactured using Fairchild's Quiet Series technology to minimize noise during switching operations.
SN74ACT573DBR
When the Latch Enable (LE) input transitions from HIGH to LOW, the latches store the information present on the D-type inputs at that moment. Data enters the latches transparently when LE is HIGH.
The OE input controls the 3-STATE output buffers. When OE is LOW, the buffers are enabled. When OE is HIGH, the outputs enter a high impedance mode, which does not interfere with entering new data into the latches.
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