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74AHC164D,118 is listed in the Shift Registers range at ChipApex. The manufacturer field lists Nexperia USA Inc.. Its product description is IC 8BIT SRLIN/PAROUT REG 14SOIC. Review the specifications below when checking this part for your BOM.
The Nexperia 74AHC164D,118 is an 8-bit serial-in/parallel-out shift register housed in a 14-lead SO plastic small outline package (SOT108-1). It operates within a supply voltage range of 2.0 V to 5.5 V and supports ambient temperatures from -40 °C to +125 °C. The device features two serial data inputs (DSA and DSB) that function as active HIGH enables for data entry through the other input. Data shifts on LOW-to-HIGH clock transitions, while an active LOW master reset clears all outputs. Inputs are overvoltage tolerant up to 5.5 V.
Verify the specific ordering suffix matches the required package type, as the 74AHC164 family includes multiple options such as TSSOP14 and DHVQFN14. Confirm the temperature range specification aligns with system requirements, noting the standard -40 °C to +125 °C rating. Ensure compatibility with the intended logic family levels, specifically CMOS for the AHC variant.
Select this component when an 8-bit shift register with parallel output is required in a surface-mount SOIC package. The AHC series offers high noise immunity and balanced propagation delays suitable for general digital logic. Consider the AHCT variant if TTL input levels are necessary instead of CMOS levels. Verify power dissipation limits against the total load capacitance and operating frequency.
This part belongs to the Nexperia 74AHC/AHCT164 family of 8-bit serial-in/parallel-out shift registers. The 'D' designation indicates the SO14 plastic small outline package (SOT108-1), distinguishing it from the PW (TSSOP14) or BQ (DHVQFN14) package variants. The '118' suffix typically denotes reel packaging specifications.
The device has two serial data inputs, DSA and DSB. Either input can serve as an active HIGH enable for data entry through the other input, allowing flexible serial data loading configurations.
Data is shifted into the register on the LOW-to-HIGH transitions of the clock (CP) input.
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