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Product Detailed Parameters
- Description:IC GATE NAND 1CH 2-INP 5TSSOP
- Series:74AUP
- Mfr:Nexperia USA Inc.
- Package:Tape & Reel (TR),Cut Tape (CT)
- Logic Type:NAND Gate
- Number of Circuits:1
- Number of Inputs:2
- Features:-
- Voltage - Supply:0.8V ~ 3.6V
- Current - Quiescent (Max):500 nA
- Current - Output High, Low:4mA, 4mA
- Input Logic Level - Low:0.7V ~ 0.9V
- Input Logic Level - High:1.6V ~ 2V
- Max Propagation Delay @ V, Max CL:6.5ns @ 3.3V, 30pF
- Operating Temperature:-40°C ~ 125°C
- Mounting Type:Surface Mount
- Supplier Device Package:5-TSSOP
- Package / Case:5-TSSOP, SC-70-5, SOT-353
- Grade:-
- Qualification:-
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Overview
The Nexperia 74AUP1G00GW,125 is a single 2-input NAND gate in the AUP logic family. It operates within a supply voltage range of 0.8 V to 3.6 V and features Schmitt-trigger inputs for noise immunity. The device supports partial power-down applications via IOFF circuitry. It is housed in a TSSOP5 (SOT353-1) package with five leads and a body width of 1.25 mm. Operating temperatures extend from -40 °C to +125 °C.
Feature Summary
- Schmitt-trigger action at all inputs ensures tolerance to slower input rise and fall times.
- IOFF circuitry disables outputs during power-down to prevent damaging backflow currents.
- ESD protection exceeds 5000 V under Human Body Model testing and 1000 V under Charged Device Model testing.
Applications
- Partial power-down mode operation
- Mixed-signal signal processing
- Low-power digital logic circuits
Procurement Notes
Verify that the ordering suffix matches the required package type, as the base part number covers multiple options. Confirm the temperature grade aligns with system requirements. Ensure compliance with JEDEC standards relevant to the specific operating voltage range. Check for RoHS and REACH status before finalizing procurement.
Selection Notes
Select this component when low static power consumption and high noise immunity are critical. The wide supply voltage range allows flexibility across various logic levels. Verify that the TSSOP5 package dimensions fit the available PCB space. Consider the propagation delay characteristics relative to the target clock frequencies.
Part Context
This device belongs to the 74AUP series of low-power CMOS logic gates. The AUP family is designed for applications requiring reduced power dissipation while maintaining performance. The 74AUP1G00 specifically implements a two-input NAND function within a compact single-gate configuration.
Replacement Considerations
Check for other packages within the same 74AUP1G00 family if the TSSOP5 form factor is unsuitable. Verify pinout compatibility before substituting with devices from other manufacturers.
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