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Product Detailed Parameters
- Description:IC GATE NAND 1CH 2-INP 5TSSOP
- Series:74AUP
- Mfr:Nexperia USA Inc.
- Package:Tape & Reel (TR),Cut Tape (CT)
- Logic Type:NAND Gate
- Number of Circuits:1
- Number of Inputs:2
- Features:Schmitt Trigger
- Voltage - Supply:0.8V ~ 3.6V
- Current - Quiescent (Max):500 nA
- Current - Output High, Low:4mA, 4mA
- Input Logic Level - Low:0.1V ~ 0.88V
- Input Logic Level - High:0.6V ~ 2.29V
- Max Propagation Delay @ V, Max CL:7.8ns @ 3.3V, 30pF
- Operating Temperature:-40°C ~ 125°C
- Mounting Type:Surface Mount
- Supplier Device Package:5-TSSOP
- Package / Case:5-TSSOP, SC-70-5, SOT-353
- Grade:-
- Qualification:-
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Overview
The Nexperia 74AUP1G132GW,125 is a single 2-input NAND gate with Schmitt-trigger inputs housed in a TSSOP5 (SOT353-1) package. It operates within a supply voltage range of 0.8 V to 3.6 V and supports an ambient temperature range from -40 °C to +125 °C. The device features low static power consumption with a maximum ICC of 0.9 μA at 25 °C. Propagation delay ranges from 1.4 ns to 6.2 ns depending on load capacitance and voltage. Inputs are overvoltage tolerant up to 3.6 V, and the component includes IOFF circuitry for partial power-down applications.
Feature Summary
- Schmitt-trigger action provides tolerance for slow input rise and fall times.
- IOFF circuitry disables outputs to prevent damaging backflow current during power-down.
- High noise immunity with low overshoot and undershoot characteristics.
Applications
- Wave and pulse shaping
- Astable multivibrator circuits
- Monostable multivibrator circuits
Procurement Notes
Verify the specific ordering suffix matches the required package variant. Confirm that the procurement channel sources directly from authorized distributors or Nexperia to ensure product authenticity. Check for recent Product Change Notifications regarding marking or assembly updates. Ensure compliance with RoHS directives and JEDEC standards relevant to the target application environment.
Selection Notes
Select this component when a compact NAND gate with hysteresis is required for low-voltage logic systems. The TSSOP5 package offers a small footprint suitable for space-constrained designs. Consider the propagation delay specifications relative to the system clock speed and load capacitance requirements. Verify that the operating voltage aligns with the 0.8 V to 3.6 V specification range.
Part Context
This part belongs to the 74AUP1G series of ultra-low-power single-gate logic devices. The AUP series is designed for applications requiring minimal power consumption across a wide voltage range. The GW suffix specifically denotes the TSSOP5 plastic thin shrink small outline package with five leads.
Replacement Considerations
Direct replacements include other 74AUP1G132 variants with different packages such as 74AUP1G132GM, 74AUP1G132GN, 74AUP1G132GS, 74AUP1G132GX, or 74AUP1G132GZ. Cross-series substitution requires verification of voltage levels and pin compatibility.
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