74AUP1G38GM,115

$0.06

Description：IC GATE NAND
Series：*
Mfr：Nexperia USA Inc.
Package：Bulk

SKU:3832bf6a2beb Category: Gates and Inverters Brand: Nexperia USA Inc.

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Product introduction

Product Detailed Parameters

Description：IC GATE NAND
Series：*
Mfr：Nexperia USA Inc.
Package：Bulk
Logic Type：-
Number of Circuits：-
Number of Inputs：-
Features：-
Voltage - Supply：-
Current - Quiescent (Max)：-
Current - Output High, Low：-
Input Logic Level - Low：-
Input Logic Level - High：-
Max Propagation Delay @ V, Max CL：-
Operating Temperature：-
Mounting Type：-
Supplier Device Package：-
Package / Case：-
Grade：-
Qualification：-

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74AUP1G38GM,115

Overview

The 74AUP1G38GM,115 is a single-channel NAND gate from the Nexperia 74AUP series. It operates on a supply voltage range of 0.8 V to 3.6 V with a maximum static current of 500 nA. The device features open-drain outputs capable of sourcing and sinking up to 4 mA. Logic low levels are defined between 0.7 V and 0.9 V, while logic high levels range from 1.6 V to 2 V. Propagation delay is specified at 12.7 ns when operating at 3.3 V with a 30 pF load. It functions within a temperature range of -40°C to +125°C and utilizes a 6-XSON (SOT886) surface-mount package.

Feature Summary

Open-drain output configuration for flexible interfacing
Low power consumption across wide voltage range
High noise immunity compliant with JEDEC standards

Applications

General-purpose digital logic processing
Mixed-signal circuit interfaces
Embedded system control logic

Procurement Notes

Verify the specific ordering suffix against official Nexperia documentation to confirm package type and tape-and-reel specifications. Confirm that the requested part number matches the exact electrical characteristics required for the target application environment. Cross-reference the manufacturer's latest datasheet to ensure compliance with current environmental directives and pinout configurations before finalizing procurement orders.

Selection Notes

Select this component for applications requiring low-voltage operation down to 0.8 V and minimal static power dissipation. The open-drain output allows for wired-AND connections and level shifting. Ensure the design accommodates the specific propagation delay and output drive capabilities defined in the datasheet for reliable signal integrity at the intended operating frequency.

Part Context

This component belongs to the 74AUP family of advanced ultra-low-power CMOS logic devices. It provides a single two-input NAND function in a compact surface-mount package. The series is designed for battery-powered and portable electronics where energy efficiency and small form factors are critical constraints.