74AUP1G38GW,125

74AUP1G38GW,125

$0.14
  • Description:IC GATE NAND 1CH 2-INP 5TSSOP
  • Series:74AUP
  • Mfr:Nexperia USA Inc.
  • Package:Tape & Reel (TR),Cut Tape (CT)

SKU:95697b99c4df Category: Brand:

  
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Product Detailed Parameters

  • Description:IC GATE NAND 1CH 2-INP 5TSSOP
  • Series:74AUP
  • Mfr:Nexperia USA Inc.
  • Package:Tape & Reel (TR),Cut Tape (CT)
  • Logic Type:NAND Gate
  • Number of Circuits:1
  • Number of Inputs:2
  • Features:Open Drain
  • Voltage - Supply:0.8V ~ 3.6V
  • Current - Quiescent (Max):500 nA
  • Current - Output High, Low:-, 4mA
  • Input Logic Level - Low:0.7V ~ 0.9V
  • Input Logic Level - High:1.6V ~ 2V
  • Max Propagation Delay @ V, Max CL:12.7ns @ 3.3V, 30pF
  • Operating Temperature:-40°C ~ 125°C
  • Mounting Type:Surface Mount
  • Supplier Device Package:5-TSSOP
  • Package / Case:5-TSSOP, SC-70-5, SOT-353
  • Grade:-
  • Qualification:-

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74AUP1G38GW,125

Overview

The Nexperia 74AUP1G38GW,125 is a single 2-input NAND gate with an open-drain output, housed in a TSSOP5 (SOT353-1) package. It operates within a supply voltage range of 0.8 V to 3.6 V and supports ambient temperatures from -40 °C to +125 °C. The device features Schmitt-trigger inputs for noise immunity and includes IOFF circuitry for partial power-down applications. Static current consumption is low, with ICC maximums ranging from 0.5 μA at 25 °C to 1.4 μA at +125 °C across the voltage range.

Feature Summary

  • Schmitt-trigger action on all inputs ensures tolerance for slower input rise and fall times.
  • IOFF circuitry disables outputs during power-down to prevent damaging backflow currents.
  • ESD protection exceeds 5000 V for Human Body Model and 1000 V for Charged Device Model.
  • Complies with JEDEC standards covering supply voltages from 0.8 V to 3.6 V.

Applications

  • Partial power-down mode operation
  • Low-power digital logic circuits
  • Noise-immune signal processing

Procurement Notes

Verify the specific ordering suffix matches the required temperature range and package variant. Confirm that the open-drain output configuration aligns with the system pull-up requirements. Ensure design compliance with the specified absolute maximum ratings to avoid permanent damage. Check for any recent product change notices regarding marking codes or package dimensions.

Selection Notes

Select this component when a single NAND function with open-drain capability is required in a minimal footprint. The wide supply voltage range makes it suitable for mixed-voltage systems. Consider the thermal derating characteristics if operating near the upper temperature limits. Verify that the input voltage levels remain within the recommended operating conditions for the chosen supply voltage.

Part Context

This device belongs to the 74AUP series of low-power CMOS logic gates. The AUP family is designed for ultra-low power consumption while maintaining high speed performance. The GW suffix specifically denotes the TSSOP5 plastic thin shrink small outline package with a body width of 1.25 mm. This packaging option provides a compact solution for space-constrained printed circuit board designs.

Replacement Considerations

Direct pin-compatible replacements must maintain the 2-input NAND logic function and open-drain output structure. Verify that alternative components support the same 0.8 V to 3.6 V supply range and Schmitt-trigger input specifications. Ensure the replacement package matches the SOT353-1 footprint and thermal characteristics.

74AUP1G38GW,12574AUP1G38GW,125
$0.14
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