74AUP1G885GF,115

Overview

The Nexperia 74AUP1G885GF,115 is a low-power dual function gate housed in an 8-XSON (SOT1203) package. It features three inputs (A, B, C) and two outputs (1Y, 2Y). Output 1Y implements the Boolean function A × C, while output 2Y implements A × B + A × C. The device operates on a supply voltage range of 0.8 V to 3.6 V with a maximum static supply current of 0.9 µA at -40 °C to +85 °C. Propagation delay ranges from 2.1 ns to 4.2 ns depending on load capacitance and temperature.

Feature Summary

• Schmitt-trigger action at all inputs provides tolerance for slower input rise and fall times.
• IOFF circuitry enables partial power-down mode by disabling outputs to prevent damaging backflow currents.
• High noise immunity with overvoltage tolerant inputs up to 3.6 V.

Applications

• Partial power down applications requiring backflow current prevention
• Logic circuits requiring Schmitt-trigger input tolerance
• Low-power CMOS logic designs

Procurement Notes

Verify the specific suffix GF corresponds to the SOT1203 XSON8 package variant. Confirm the component status as End-of-Life (EOL) based on manufacturer notices. Ensure design-in validation accounts for the specified operating temperature range and electrical characteristics prior to final procurement decisions.

Selection Notes

Select this component when a single IC must provide two distinct dual-function logic operations within a minimal footprint. The choice is driven by the requirement for low static power consumption across a wide voltage range and the need for robust input signal conditioning via Schmitt triggers.

Part Context

This part belongs to the 74AUP series of ultra-low-power CMOS logic devices manufactured by Nexperia. It is designed for portable and battery-operated applications where minimizing power dissipation is critical. The device utilizes advanced semiconductor processes to achieve high performance at low voltages.

Replacement Considerations

The 74AUP1G885GS,115 is listed as a manufacturer-recommended alternative. Verify pinout compatibility and package dimensions before substitution.

FAQ

What are the Boolean functions implemented by the outputs?

Output 1Y performs the AND operation A × C. Output 2Y performs the function A × B + A × C.

How does the IOFF feature benefit the circuit?

The IOFF circuitry disables the outputs when the device is powered down, preventing potentially damaging backflow current through the device.