74AUP1G885GT,115

Overview

The Nexperia 74AUP1G885GT,115 is a low-power dual function gate housed in an XSON8 (SOT833-1) package. It operates within a supply voltage range of 0.8 V to 3.6 V and supports ambient temperatures from -40 °C to +125 °C. The device features Schmitt-trigger inputs for noise tolerance and includes IOFF circuitry for partial power-down applications. Static supply current is limited to a maximum of 1.4 µA across the full temperature range.

Feature Summary

• Implements Boolean logic functions 1Y = A × C and 2Y = A × B + A × C
• Schmitt-trigger action at all inputs ensures tolerance to slow signal transitions
• IOFF circuitry disables outputs to prevent damaging backflow currents during power-down

Applications

• Partial power-down mode operation
• Low-power digital logic circuits
• Noise-immune signal processing

Procurement Notes

Verify that the ordering suffix matches GT,115 to confirm the XSON8 package type. Confirm the revision history indicates Rev. 13 or later to ensure compliance with current JEDEC ESD standards. Check product status to verify active production availability before finalizing design-in decisions.

Selection Notes

Select this component when a single IC must provide two distinct AND-based logic functions. The wide supply voltage range allows compatibility with various low-voltage logic families. Ensure input transition rates do not exceed 200 ns/V to maintain proper Schmitt-trigger functionality.

Part Context

This part belongs to the 74AUP series of ultra-low-power CMOS logic devices. It is specifically designed as a dual-function gate, combining two logic operations into one compact package. The GT suffix identifies the specific XSON8 leadless package variant suitable for space-constrained surface-mount designs.

Replacement Considerations

74AUP1G885DC,115

FAQ

What are the specific Boolean functions implemented by the outputs?

Output 1Y implements the function A × C, while output 2Y implements the function A × B + A × C.

How does the device handle partial power-down conditions?

The integrated IOFF circuitry disables the outputs when VCC is powered down, preventing potentially damaging backflow current through the device.