74AUP1G97GW,125

74AUP1G97GW,125

$0.28
  • Description:IC CONFIG MULT-FUNC GATE 6TSSOP
  • Series:74AUP
  • Mfr:Nexperia USA Inc.
  • Package:Tape & Reel (TR),Cut Tape (CT)

SKU:16aa0f525188 Category: Brand:

  
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Product Detailed Parameters

  • Description:IC CONFIG MULT-FUNC GATE 6TSSOP
  • Series:74AUP
  • Mfr:Nexperia USA Inc.
  • Package:Tape & Reel (TR),Cut Tape (CT)
  • Logic Type:Configurable Multiple Function
  • Number of Circuits:1
  • Number of Inputs:3
  • Schmitt Trigger Input:Yes
  • Output Type:Single-Ended
  • Current - Output High, Low:4mA, 4mA
  • Voltage - Supply:0.8V ~ 3.6V
  • Operating Temperature:-40°C ~ 125°C
  • Grade:-
  • Qualification:-
  • Mounting Type:Surface Mount
  • Package / Case:6-TSSOP, SC-88, SOT-363
  • Supplier Device Package:6-TSSOP

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74AUP1G97GW,125

Overview

The Nexperia 74AUP1G97GW,125 is a single configurable multiple function gate housed in a TSSOP6 (SOT363-2) package. It operates on a supply voltage range of 0.8 V to 3.6 V with an ambient temperature specification from -40 °C to +125 °C. The device features Schmitt-trigger inputs and includes IOFF circuitry for partial power-down applications. Static supply current is limited to a maximum of 1.4 μA at the upper temperature limit. Propagation delay ranges from 1.5 ns to 5.1 ns depending on load capacitance and voltage.

Feature Summary

  • Configurable logic functions including MUX, AND, OR, NAND, NOR, inverter, and buffer via three-bit input selection
  • IOFF circuitry prevents backflow current during partial power-down mode
  • Schmitt-trigger inputs provide high noise immunity and low overshoot
  • ESD protection exceeds 5000 V under HBM and 1000 V under CDM standards

Applications

  • Partial power-down systems requiring output disablement
  • Low-power CMOS logic designs
  • Signal routing and multiplexing applications
  • Level shifting between compatible voltage domains

Procurement Notes

Verify the SOT363-2 package designation matches the required footprint. Confirm the -40 °C to +125 °C temperature rating aligns with system thermal constraints. Ensure design accounts for the specified IOFF leakage characteristics if operating in power-down states. Cross-reference marking code 'aV' for quality assurance.

Selection Notes

Select this component when a single gate must perform multiple logic roles to save board space. The wide voltage range supports various low-voltage logic families. Verify that the 20 mA output drive capability meets load requirements. Consider the propagation delay limits for high-speed signal integrity needs.

Part Context

This part belongs to the Nexperia 74AUP1G series of ultra-low power logic gates. The AUP family is designed for battery-powered devices requiring minimal static power consumption. The GW suffix specifically denotes the thin shrink small outline plastic package with six leads.

Replacement Considerations

Direct pin-compatible alternatives include 74AUP1G97GM, 74AUP1G97GN, 74AUP1G97GS, and 74AUP1G97GX. These variants share identical electrical specifications but differ in physical package dimensions.

74AUP1G97GW,12574AUP1G97GW,125
$0.28
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