74AUP1T00GXH

Overview

The Nexperia 74AUP1T00GXH is a low-power 2-input NAND gate with voltage-level translator in an X2SON5 (SOT1226-3) package. It operates from a supply voltage of 2.3 V to 3.6 V, accepting inputs up to 3.6 V. Static power consumption is 1.5 μA maximum at -40 °C to +85 °C and 3.5 μA at -40 °C to +125 °C. Propagation delay ranges from 0.5 ns to 11.9 ns depending on load capacitance and temperature. The device includes IOFF circuitry for partial power-down mode operation.

Feature Summary

• Provides single 2-input NAND logic function with Schmitt trigger inputs for noise immunity.
• Supports logic-level translation between 1.8 V CMOS signals and 2.5 V or 3.3 V supplies.
• Includes IOFF circuitry to disable outputs and prevent backflow current during power-down.
• Offers high ESD protection exceeding 5000 V (HBM) and 1000 V (CDM).

Applications

• Logic-level translation applications
• Partial power-down systems
• Battery-operated devices

Procurement Notes

Verify the specific ordering suffix 'H' against official Nexperia documentation to confirm reel packaging specifications. Ensure the component matches the X2SON5 package outline SOT1226-3 dimensions. Confirm that the intended application environment falls within the specified operating temperature range of -40 °C to +125 °C.

Selection Notes

Select this component when a compact 2-input NAND gate with integrated voltage translation is required. The X2SON5 package provides a small footprint suitable for space-constrained designs. Consider the propagation delay variations across different load capacitances and temperature ranges during circuit design.

Part Context

This part belongs to the 74AUP series of low-power CMOS logic devices. The AUP family is characterized by wide supply voltage ranges and low static power consumption. The 74AUP1T00 specifically integrates voltage translation capabilities, distinguishing it from standard NAND gates without level-shifting features.

Replacement Considerations

Check for 74AUP1T00GW if TSSOP5 packaging is acceptable. Verify functional equivalence for any alternative vendors offering similar 2-input NAND gates with voltage translation in comparable packages.