74AUP1T97GM,132

$0.09

Description：NEXPERIA 74AUP1T97GM - LOGIC CIR
Series：*
Mfr：Nexperia USA Inc.
Package：Bulk

SKU:7c7f72592ddb Category: Translators, Level Shifters Brand: Nexperia USA Inc.

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Product introduction

Product Detailed Parameters

Description：NEXPERIA 74AUP1T97GM - LOGIC CIR
Series：*
Mfr：Nexperia USA Inc.
Package：Bulk
Translator Type：-
Channel Type：-
Number of Circuits：-
Channels per Circuit：-
Input Signal：-
Output Signal：-
Output Type：-
Data Rate：-
Operating Temperature：-
Features：-
Mounting Type：-
Package / Case：-
Supplier Device Package：-
Voltage - VCCA：-
Voltage - VCCB：-
Grade：-
Qualification：-

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74AUP1T97GM,132

Overview

The Nexperia 74AUP1T97GM,132 is a low-power configurable gate with voltage-level translator. It features Schmitt-trigger inputs and can be configured as MUX, AND, OR, NAND, NOR, inverter, or buffer using a 3-bit input. The device operates within a wide supply voltage range of 2.3 V to 3.6 V. It includes I_OFF circuitry for partial power-down applications to prevent backflow current. ESD protection exceeds 5000 V (HBM) and 1000 V (CDM).

Feature Summary

Configurable multiple-function gate with level translating capabilities.
Low threshold Schmitt trigger inputs allow driving by 1.8 V logic levels in 3.3 V applications.
I_OFF circuitry provides partial power-down mode operation to disable outputs.

Applications

Partial power-down applications requiring backflow current prevention.
Voltage-level translation between 1.8 V and 3.3 V logic systems.
General-purpose configurable logic functions in low-power CMOS designs.

Procurement Notes

Verify the specific suffix GM,132 against official Nexperia documentation to confirm package type and reel specifications. Ensure compatibility with required operating temperatures and ESD protection standards for the target application environment before finalizing procurement decisions.

Selection Notes

Select this component when a single gate requires multiple logic function configurations via external inputs. It is suitable for designs needing voltage translation between 1.8 V and 3.3 V domains while maintaining low static power consumption. Verify that the 3-bit configuration interface fits the available pin count and control logic resources.

Part Context

This part belongs to the 74AUP series of ultra-low-power CMOS logic devices. The AUP family is designed for applications requiring high speed and low power consumption across a wide voltage range. The 74AUP1T97 specifically integrates level-shifting capabilities into a configurable gate architecture.