74AUP1T98GF,132

Overview

The Nexperia 74AUP1T98GF,132 is a low-power configurable gate with voltage-level translator featuring Schmitt-trigger inputs. It supports supply voltages from 2.3 V to 3.6 V and operates within an ambient temperature range of -40 °C to +125 °C. The device includes IOFF circuitry for partial power-down applications. It provides high noise immunity and complies with JEDEC standards JESD8-12 through JESD8C.

Feature Summary

• Configurable multiple function gate supporting MUX, AND, OR, NAND, NOR, inverter, and buffer logic functions via 3-bit input selection
• Level translating capability with low threshold Schmitt trigger inputs allowing direct driving by 1.8 V logic levels in 3.3 V applications
• IOFF circuitry disables the output during power-down to prevent damaging backflow current
• Overvoltage tolerant inputs up to 3.6 V with ESD protection exceeding 5000 V (HBM) and 1000 V (CDM)

Applications

• Partial power-down mode operation in mixed-voltage systems
• Voltage level translation between 1.8 V and 3.3 V domains
• Configurable logic implementation in space-constrained designs

Procurement Notes

Verify the specific package type associated with the GF suffix against official Nexperia documentation, as revision history indicates package availability changes. Confirm that the component meets the required operating temperature range and JEDEC compliance standards for the intended application environment before finalizing procurement.

Selection Notes

Select this component when a single IC must perform multiple logic functions or act as a voltage translator in low-power designs. Ensure the design accommodates the 2.3 V to 3.6 V supply range and utilizes the configurable inputs to define the desired logic state. Consider the IOFF feature if partial power-down functionality is required to minimize static power consumption.

Part Context

The 74AUP1T98 belongs to the Nexperia 74AUP family of ultra-low-power CMOS logic devices. This series is designed for applications requiring minimal power dissipation while maintaining high noise immunity. The device integrates configurable logic gates with built-in level shifting capabilities, eliminating the need for separate translator components in mixed-voltage interfaces.

Replacement Considerations

Nexperia 74AUP1T98GM,132; Nexperia 74AUP1T98GN,132; Nexperia 74AUP1T98GS,132; Nexperia 74AUP1T98GW,125.