74AUP1Z04GM,132

Overview

The Nexperia 74AUP1Z04GM,132 is a low-power crystal driver with enable and internal resistor. It operates within a supply voltage range of 0.8 V to 3.6 V and supports an ambient temperature range from -40 °C to +125 °C. The device features Schmitt trigger action on the EN input for tolerance to slow rise and fall times. It includes IOFF circuitry for partial power-down mode operation at output Y. The component utilizes XSON6 (SOT886) packaging.

Feature Summary

• Integrated bias resistor provides negative feedback to set the inverter bias point near mid-supply.
• Enable input controls low power disable mode, pulling X1 HIGH via RPU and setting X2 LOW.
• IOFF circuitry prevents damaging backflow current when the device is powered down.
• Schmitt trigger action ensures tolerance to slower input transition rates across the full voltage range.

Applications

• Crystal controlled oscillator circuits
• Clock pulse generators requiring frequency stability
• Low power dissipation applications

Procurement Notes

Verify the specific ordering suffix

Selection Notes

Select this component for designs requiring a dedicated crystal driver with integrated biasing and enable functionality. Ensure the system operates within the specified 0.8 V to 3.6 V supply range and -40 °C to +125 °C temperature limits. Confirm that the XSON6 package dimensions fit the PCB layout constraints.

Part Context

This part belongs to the 74AUP1Z04 series, which includes variants in TSSOP6, XSON6, and other packages. The GM suffix specifically denotes the XSON6 (SOT886) package type. Other series members share similar electrical characteristics but differ in physical footprint and pinout configuration.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation. Verify compatibility with existing design requirements before considering alternative components.

FAQ

What is the function of the EN input?

The EN input is an active LOW enable input. Driving it HIGH puts the device in a low power disable mode.

How does the device handle partial power-down?

The IOFF circuitry disables the output Y, preventing damaging backflow current through the device when it is powered down.