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The Nexperia 74AUP2G58DPJ is a low-power dual configurable multiple function gate housed in a TSSOP10 (SOT552-1) package. It operates within a supply voltage range of 0.8 V to 3.6 V and supports an ambient temperature range from -40 °C to +125 °C. Each gate utilizes Schmitt-trigger inputs and three control bits to configure logic functions including AND, OR, NAND, NOR, XOR, buffer, and inverter. The device features IOFF circuitry for partial power-down applications, ensuring low static power consumption with a maximum ICC of 0.9 μA at extended temperatures.
Verify the specific ordering suffix DPJ corresponds to the TSSOP10 package variant when sourcing. Confirm that the component status remains active or qualified for production, as availability may change. Ensure design-in documentation references the correct SOT552-1 mechanical dimensions for PCB layout compatibility.
Select this component when space-constrained designs require multiple logic functions within a single package. The AUP series offers lower power dissipation compared to older families while maintaining compatibility with 3.3 V systems. Verify that the required propagation delay characteristics align with the target clock frequencies under the specific load capacitance conditions of the application.
This part belongs to the Nexperia 74AUP family of ultra-low-power CMOS logic devices. The 74AUP2G58 specifically provides two independent configurable gates, allowing designers to replace multiple discrete logic ICs. The DPJ suffix identifies the thin shrink small outline package variant, distinguishing it from other form factors like XQFN available in the same logical family.
Direct replacements include the 74AUP2G58GU for the XQFN10 package variant. Designers must verify pinout compatibility and thermal performance differences between the TSSOP10 and alternative packages before substitution.