74AUP2G97DPJ

Overview

The Nexperia 74AUP2G97DPJ is a low-power dual configurable multiple function gate housed in a TSSOP10 (SOT552-1) package. It operates within a supply voltage range of 0.8 V to 3.6 V and supports an ambient temperature range from -40 °C to +125 °C. The device features Schmitt-trigger inputs and includes IOFF circuitry for partial power-down applications. Static characteristics specify a maximum supply current of 0.9 μA at 25 °C and 1.4 μA at elevated temperatures. Dynamic performance shows propagation delays ranging from 1.9 ns to 4.3 ns depending on load capacitance and voltage.

Feature Summary

• Configurable logic functions including MUX, AND, OR, NAND, NOR, inverter, and buffer using 3-bit input selection
• IOFF circuitry prevents damaging backflow current during partial power-down states
• Schmitt-trigger inputs provide high noise immunity with defined hysteresis
• ESD protection exceeds 5000 V per HBM and 1000 V per CDM standards

Applications

• Partial power-down system architectures requiring backflow current prevention
• Low-voltage digital signal routing and buffering
• Configurable logic implementation in space-constrained PCB designs
• Noise-immune data path conditioning in mixed-signal environments

Procurement Notes

Verify the ordering suffix DPJ corresponds to the TSSOP10 plastic thin shrink small outline package with SOT552-1 designation. Confirm that the specific batch matches the Rev. 4 product data sheet dated 1 August 2023. Ensure environmental compliance aligns with RoHS3 specifications. Check for any recent Product Change Notifications regarding marking codes or assembly processes before finalizing procurement orders.

Selection Notes

Select this component when dual configurable gates are required in a minimal footprint. The TSSOP10 package accommodates two independent gates with three control inputs each. Consider the 0.8 V minimum operating voltage for ultra-low power applications. Verify that the 4 mA output drive capability meets the load requirements. Evaluate the propagation delay specifications against the target clock frequencies for the intended application speed.

Part Context

This device belongs to the Nexperia 74AUP series, characterized by low power consumption and wide supply voltage operation. The 74AUP2G97 specifically provides dual configurable gates, distinguishing it from fixed-function logic families. It utilizes advanced CMOS technology to achieve high noise immunity while maintaining low static power dissipation across the entire operational voltage range.

Replacement Considerations

Public confirmed substitute part numbers include 74AUP2G97GU for the XQFN10 package variant.