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The 74AUP3G3404GD125 is a low-power dual buffer and single inverter from the Nexperia 74AUP series. It operates across a wide supply voltage range of 0.8 V to 3.6 V. The device features Schmitt trigger action at all inputs, providing tolerance for slower input rise and fall times. It includes IOFF circuitry that disables outputs during partial power-down mode to prevent damaging backflow currents. Static power consumption is specified as maximum 0.9 μA at -40 °C to +85 °C. Latch-up performance exceeds 100 mA per JESD 78B Class II.
Verify the specific package suffix GD125 against the manufacturer's ordering information table. Confirm the temperature range matches the required application environment. Ensure the component status is active before procurement. Cross-reference the datasheet revision date to confirm the latest specifications are being used.
Select this component when a combination of buffering and inversion is required in a single package. The wide voltage range supports various logic families. The Schmitt trigger feature is critical for noisy environments or slow signals. Verify that the 8-lead package fits the available PCB space constraints.
This part belongs to the 74AUP family of ultra-low-power CMOS logic devices. The 74AUP3G3404 specifically integrates two buffers and one inverter. It is designed for portable and battery-operated applications due to its low power characteristics. The device is manufactured by Nexperia.
Check for direct pin-compatible alternatives within the same 74AUP family. Verify if other packages like XSON or VSSOP offer better thermal or spatial performance. Ensure any substitute maintains the IOFF functionality if partial power-down is required.