SEARCH
— IC芯片 | 连接器 | 传感器 | 被动器件 —
The Nexperia 74AUP3G3404GMH is a low-power dual buffer and single inverter from the AUP logic family. It operates across a wide supply voltage range of 0.8 V to 3.6 V with Schmitt trigger inputs for noise immunity. The device features IOFF circuitry for partial power-down applications, preventing backflow current. Static supply current is limited to 1.4 μA maximum at -40 °C to +125 °C. Propagation delay ranges from 1.0 ns to 5.5 ns depending on load capacitance and voltage. It supports ESD protection exceeding 5000 V (HBM) and complies with JEDEC standards.
Verify the specific suffix GMH against official Nexperia documentation to confirm package type and tape/reel specifications. Ensure compatibility with design requirements regarding lead-free status and halogen-free definitions. Confirm RoHS compliance and REACH registration status prior to integration. Check for any recent product change notices affecting marking or assembly locations.
Select this component when designing systems requiring mixed buffer and inversion functions in a minimal footprint. The AUP series offers superior speed-to-power efficiency compared to older families. Verify that input voltages do not exceed the absolute maximum ratings during power-up sequences. Consider the thermal derating curves if operating near the upper temperature limits.
This device belongs to the Nexperia 74AUP3Gxx series of ultra-low-power logic ICs. It integrates three independent logic gates into a single package, optimizing board space. The AUP family is designed for battery-powered applications where energy conservation is critical. It replaces older generation logic families while maintaining pin-out compatibility in many cases.
Check for direct replacements such as 74AUP3G3404DC or 74AUP3G3404GT if the GMH package is unavailable. Ensure substitute parts match the required operating temperature range and electrical characteristics. Verify that alternative packages maintain the same pin configuration for drop-in replacement.