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The onsemi 74F673ASC is a 16-bit Serial-In, Serial/Parallel-Out shift register housed in a 24-lead Small Outline Integrated Circuit (SOIC) package. It operates within a supply voltage range of +4.5V to +5.5V and supports an ambient temperature range of 0°C to +70°C. The device features a common serial data I/O pin that functions as either a serial input or a 3-state serial output. Key electrical parameters include a maximum clock frequency of 85 MHz at the upper operating temperature limit, with propagation delays ranging from 2.5 ns to 15.0 ns depending on the specific signal path.
Verify the exact ordering code suffix against manufacturer documentation to confirm package type and tape/reel availability. Ensure the component meets the required industrial temperature specifications for your application environment. Cross-reference the datasheet revision date to confirm compatibility with current design standards. Confirm RoHS compliance status if restricted substances are a constraint for your manufacturing process.
Select this component when a 16-bit shift register with parallel output capability is required in a surface-mount format. The SOIC-24 package offers a compact footprint suitable for space-constrained designs. Consider the 3-state output feature if bus sharing or tri-stating is necessary for system integration. Verify that the logic family voltage levels align with the rest of the digital circuitry.
This part belongs to the 74F logic family, known for high-speed performance compared to standard TTL. The 74F673A variant specifically provides serial-in, serial/parallel-out functionality. The 'ASC' designation indicates the 24-lead SOIC package configuration manufactured by onsemi, formerly Fairchild Semiconductor.
Check for direct equivalents such as the 74F673APC (PDIP) or 74F673ASPC (narrow PDIP) if through-hole mounting is preferred. Other manufacturers producing 74F673A devices may offer compatible replacements, provided pinouts and electrical characteristics match exactly.
A HIGH signal on the Chip Select (CS) input prevents both shifting and parallel transfer, forcing the Serial Input/Output buffer into a high-impedance state.
The Store Master Reset (STMR) input is asynchronous and overrides all other inputs, forcing the Q0–Q15 outputs LOW regardless of clock or data states.
Yes, when CS and R/W are both LOW, the contents of the shift register are transferred to the storage register for parallel outputting via the STCP pulse.