74HC112D,652

74HC112D,652

$0.19
  • Description:IC FF JK TYPE DUAL 1BIT 16SO
  • Series:74HC
  • Mfr:Nexperia USA Inc.
  • Package:Bulk,Tube

SKU:f8803b6379ed Category: Brand:

  
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Product Detailed Parameters

  • Description:IC FF JK TYPE DUAL 1BIT 16SO
  • Series:74HC
  • Mfr:Nexperia USA Inc.
  • Package:Bulk,Tube
  • Function:Set(Preset) and Reset
  • Type:JK Type
  • Output Type:Complementary
  • Number of Elements:2
  • Number of Bits per Element:1
  • Clock Frequency:71 MHz
  • Max Propagation Delay @ V, Max CL:30ns @ 6V, 50pF
  • Trigger Type:Negative Edge
  • Current - Output High, Low:5.2mA, 5.2mA
  • Voltage - Supply:2V ~ 6V
  • Current - Quiescent (Iq):4 µA
  • Operating Temperature:-40°C ~ 125°C (TA)
  • Mounting Type:Surface Mount
  • Supplier Device Package:16-SO
  • Package / Case:16-SOIC (0.154", 3.90mm Width)
  • Input Capacitance:3.5 pF
  • Grade:-
  • Qualification:-

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74HC112D,652

Overview

The Nexperia 74HC112D,652 is a dual negative-edge triggered JK flip-flop housed in a 16-pin SO package. It features individual J and K inputs, asynchronous active LOW set (nSD) and reset (nRD) inputs, and complementary nQ and Q outputs. The device operates within a supply voltage range of 2V to 6V and supports an operating temperature range from -40°C to +85°C. Inputs include clamp diodes for interfacing with voltages exceeding VCC.

Feature Summary

  • Dual negative-edge triggered JK flip-flops with independent clock control
  • Asynchronous active LOW set and reset inputs operating independently of the clock
  • Schmitt-trigger action on the clock input for tolerance to slow rise and fall times
  • Input clamp diodes enabling interface to voltages in excess of VCC

Applications

  • Digital state storage circuits
  • Frequency division networks
  • Shift register construction
  • Counter logic implementation

Procurement Notes

Verify the specific suffix against official Nexperia documentation to confirm package type and tape/reel specifications. Confirm RoHS compliance status and lead times directly with authorized distributors or the manufacturer. Ensure the selected variant matches the required operating temperature range and ESD protection levels for the target application environment.

Selection Notes

Select this component when dual JK functionality with asynchronous control is required. The Schmitt-triggered clock input provides robustness against signal noise. Verify that the 2V to 6V supply range aligns with the system power rails. Consider the 16-pin SO package dimensions for PCB layout constraints compared to alternative packages like TSSOP.

Part Context

This part belongs to the Nexperia 74HC series of high-speed CMOS logic devices. It implements standard JEDEC-compliant JK flip-flop functionality. The device is designed for general-purpose digital applications requiring reliable state retention and synchronous data transfer triggered by clock edges.

Replacement Considerations

Check for equivalent parts such as the 74HCT112 variant if TTL-level input compatibility is needed instead of CMOS levels. Verify pinout and electrical characteristics match before substitution.

74HC112D,65274HC112D,652
$0.19
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