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74HC373PW,112 is listed in the Latches range at ChipApex. The manufacturer field lists Nexperia USA Inc.. Its product description is IC D-TYPE TRANSP SGL 8:8 20TSSOP. Review the specifications below when checking this part for your BOM.
The Nexperia 74HC373PW,112 is an octal D-type transparent latch with 3-state outputs housed in a TSSOP20 package (SOT360-1). It features latch enable (LE) and output enable (OE) inputs. The device operates on a supply voltage range of 2.0 V to 6.0 V. Static characteristics include an input leakage current of ±1.0 μA maximum at -40 °C to +125 °C and a supply current of 160 μA maximum under the same conditions. Dynamic performance specifies a propagation delay from data input to output of 38 ns maximum at 4.5 V and -40 °C to +85 °C.
Verify component authenticity through authorized Nexperia channels or certified distributors. Confirm the specific ordering suffix matches the required package variant. Review the latest product data sheet for any updates regarding specifications or compliance standards before finalizing procurement decisions.
Select this component for designs requiring an octal latch with 3-state outputs in a TSSOP20 package. Ensure the application voltage falls within the 2.0 V to 6.0 V range. Consider the specified temperature range and ESD protection levels when evaluating suitability for the target environment.
This part belongs to the 74HC series of CMOS logic devices manufactured by Nexperia. It is functionally compatible with other industry-standard octal latches but offers specific Nexperia packaging and electrical characteristics. The PW suffix indicates the TSSOP20 plastic thin shrink small outline package.
Direct replacements include the 74HC373D,653 (SO20 package) and 74HC373BQ (DHVQFN20 package) from Nexperia. Cross-manufacturer equivalents such as SN74HC373 may be considered if pinout and electrical specifications are verified against the official datasheet.
A HIGH level on the OE input causes the outputs to assume a high-impedance OFF-state. This operation does not affect the internal state stored in the latches.
When LE is HIGH, the latches are transparent and data enters from the inputs. When LE transitions from HIGH to LOW, the information present at the inputs is stored in the latches.
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