Latches 74LVC16373ADGG,118 product image

74LVC16373ADGG,118

$0.78
  • Description:IC TRANS D-TYP LATCH 3ST 48TSSOP
  • Series:74LVC
  • Mfr:Nexperia USA Inc.
  • Package:Tape & Reel (TR),Cut Tape (CT)

SKU:7d3d182adc9f Category: Brand:

  
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74LVC16373ADGG,118 is listed in the Latches range at ChipApex. The manufacturer field lists Nexperia USA Inc.. Its product description is IC TRANS D-TYP LATCH 3ST 48TSSOP. Review the specifications below when checking this part for your BOM.

Latches specifications for 74LVC16373ADGG,118

  • Description:IC TRANS D-TYP LATCH 3ST 48TSSOP
  • Series:74LVC
  • Mfr:Nexperia USA Inc.
  • Package:Tape & Reel (TR),Cut Tape (CT)
  • Logic Type:D-Type Transparent Latch
  • Circuit:8:08
  • Output Type:Tri-State
  • Voltage - Supply:1.65V ~ 3.6V
  • Independent Circuits:2
  • Delay Time - Propagation:1ns
  • Current - Output High, Low:24mA, 24mA
  • Operating Temperature:-40°C ~ 125°C
  • Mounting Type:Surface Mount
  • Package / Case:48-TFSOP (0.240", 6.10mm Width)
  • Supplier Device Package:48-TSSOP
  • Grade:-
  • Qualification:-

Latches datasheet and documents for 74LVC16373ADGG,118

74LVC16373ADGG,118

Latches Overview

The Nexperia 74LVC16373ADGG,118 is a 16-bit D-type transparent latch with 3-state outputs housed in a TSSOP48 (SOT362-1) package. It operates on a supply voltage range of 1.2 V to 3.6 V and features inputs/outputs tolerant up to 5.5 V. The device supports two independent 8-bit sections controlled by separate latch enables (1LE, 2LE) and output enables (1OE, 2OE). It includes IOFF circuitry for partial power-down protection and Schmitt-trigger inputs for noise immunity.

Latches Feature Summary

  • Features 5 V tolerant inputs and outputs allowing direct interfacing with mixed 3.3 V and 5 V logic environments.
  • Includes IOFF circuitry that disables outputs to prevent damaging backflow current during partial power-down applications.
  • Schmitt-trigger action at all inputs provides tolerance for slower input rise and fall times.

Latches Applications

  • Mixed voltage bus architectures requiring level translation between 3.3 V and 5 V domains
  • Parallel data storage and buffering in high-speed digital systems
  • Partial power-down mode operation in portable electronic devices

Latches Procurement Notes

Verify the specific suffix '118' corresponds to the required tape-and-reel packaging configuration. Confirm the TSSOP48 body width matches your PCB footprint requirements. Ensure the design accounts for the -40 °C to +125 °C operating temperature range specified for this variant.

Latches Selection Notes

Select this component when a 16-bit latch with 5 V tolerance is required. The LVC series offers lower power consumption compared to older logic families. Verify if the bus hold feature is needed; note that standard LVC variants lack bus hold, whereas LVCH variants include it.

Latches Part Context

This part belongs to the Nexperia 74LVC/LVCH16373A family of 16-bit latches. It shares functional similarities with the 74LVCH16373ADGG but lacks the internal bus hold circuitry found in the LVCH version. Both are designed for low-voltage CMOS applications requiring high noise immunity.

Latches Replacement Considerations

The 74LVCH16373ADGG,118 is a compatible alternative within the same package, offering additional bus hold functionality on data inputs. Other 16-bit latches from different manufacturers may require pinout verification and voltage level assessment before substitution.

74LVC16373ADGG,11874LVC16373ADGG,118
$0.78
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