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74LVX373MTC is listed in the Latches range at ChipApex. The manufacturer field lists onsemi. Its product description is IC D-TYPE TRANSP SGL 8:8 20TSSOP. Review the specifications below when checking this part for your BOM.
The onsemi 74LVX373MTC is a low voltage octal transparent latch with 3-STATE outputs, housed in a 20-Lead Thin Shrink Small Outline Package (TSSOP). It operates within a supply voltage range of 2.0V to 3.6V and supports an input voltage up to 5.5V. The device features eight D-type latches that appear transparent when Latch Enable is HIGH and store data upon the HIGH-to-LOW transition of the enable signal. Propagation delays from data inputs to outputs are typically 9.7 ns at 3.3V with 15 pF load, while output enable/disable times reach 12.8 ns maximum under similar conditions.
Verify the specific package designation MTC20 corresponds to the required 20-Lead TSSOP form factor. Confirm that the operating temperature range of -40°C to +85°C aligns with environmental requirements. Ensure input signals do not exceed the absolute maximum ratings to prevent damage. Check for updated ordering codes if migrating from legacy Fairchild nomenclature containing underscores.
Select this component when designing systems requiring octal data latching with high impedance states for bus sharing. The wide input voltage tolerance facilitates mixed-voltage designs without additional level shifters. Consider the propagation delay specifications relative to system clock speeds to ensure timing margins are met across the full operating temperature range.
This device belongs to the LVX series of low voltage CMOS logic products. It succeeds earlier variants like the 74LVX373MTCX which shares similar electrical characteristics but may differ in packaging or reel specifications. The part integrates standard latch functionality optimized for modern low voltage digital environments.
Direct substitutes include other 74LVX373 variants such as MC74LVX373DWR2G or 74LVX373MTCX, provided pin compatibility and package dimensions match the design constraints.
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