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— IC芯片 | 连接器 | 传感器 | 被动器件 —
The 78Q8392LA03-CHR/F is a low power Ethernet coaxial transceiver designed as a replacement for the 78Q8392L/A02. It provides the interface between single-ended coaxial cable signals and Manchester-encoded differential logic signals, supporting IEEE 802.3 10Base5 and 10Base2 standards. The device integrates analog transmit/receive buffers, a 10 MHz oscillator, collision detection, jabber timer, and heartbeat functions. It operates on a -9V supply with non-transmitting current of 6 to 8 mA and transmitting current of 50 to 65 mA. Differential output voltage ranges from ±550 mV to ±1200 mV, with receiver startup delay at 400 to 500 ns.
Verify the specific package configuration required for the design, as the datasheet lists 16-pin DIP and 28-pin PLCC options. Confirm that the ordering suffix corresponds to the intended lead-free plastic package variant. Ensure the source document matches the Teridian Semiconductor Corporation specification for the 78Q8392L/A03 revision 1.3 to guarantee functional compatibility with existing designs.
Select this component when upgrading from the 78Q8392L/A02, requiring only a single resistor value change. Choose the appropriate package based on board space constraints, noting the thermal dissipation requirements for the VEE pins. Verify that the system supports the -9V supply voltage and accommodates the necessary isolation transformers for the AUI interface connections.
Originally manufactured by Teridian Semiconductor Corporation, this device serves as a legacy Ethernet physical layer component. Analog Devices Inc./Maxim Integrated branding may appear in distributor listings due to corporate acquisitions, but the technical specifications remain defined by the original Teridian documentation. It is distinct from modern high-speed PHYs, focusing specifically on legacy coaxial bus architectures.
The datasheet explicitly identifies the 78Q8392L/A03 as a direct replacement for the SSI/TDK/Teridian 78Q8392L/A02. Upgrading requires changing only one external resistor value. No other major circuit modifications are necessary for migration.
The receiver utilizes squelch circuitry that determines valid data via three criteria: average DC level, pulse width greater than 20 ns, and transition period less than 200 ns. Invalid signals are rejected to prevent false triggering.
The Heartbeat Enable (HBE) pin controls the collision detect heartbeat function. Grounding or leaving it open enables the heartbeat, while connecting it to VEE disables it.
A fixed 976 Ω 1% resistor connected between the RR+ and RR- pins establishes the internal operating currents. This differs from the previous generation which used a 1kΩ resistor.