954226AGLF

Application Specific Clock/Timing Overview

The Renesas 954226AGLF is a CK410M-compatible programmable clock synthesizer designed for mobile P4 systems. It operates on a single 3.3V supply and utilizes an external 14.318MHz crystal to generate CPU outputs up to 400MHz. The device provides tight ppm accuracy for Serial ATA and PCI Express interfaces. Key electrical specifications include CPU output cycle-cycle jitter of less than 85ps, PCI Express and SATA jitter under 125ps, and PCI jitter below 500ps. Frequency accuracy is specified at +/- 300ppm for CPU, PCI Express, and SATA clocks, and +/- 100ppm for USB clocks.

Application Specific Clock/Timing Feature Summary

• CK410M compatible clock synthesizer supporting Intel P4-M processors
• Generates CPU frequencies up to 400MHz with < 85ps cycle-cycle jitter
• Supports tight ppm accuracy for Serial ATA and PCI Express interfaces
• Features programmable spread spectrum percentage and frequency via SMBus

Application Specific Clock/Timing Applications

• Mobile P4 processor systems
• Intel mobile chipset designs
• Serial ATA (SATA) clock generation
• PCI Express (PCIe) clock generation

Application Specific Clock/Timing Procurement Notes

Verify the component status as obsolete or end-of-life through official manufacturer channels before procurement planning. Confirm that the specific package variant matches the design requirements, as the datasheet details both TSSOP and MLF pin configurations. Ensure external crystal load capacitors are included in the bill of materials for proper frequency tuning.

Application Specific Clock/Timing Selection Notes

Select this component for applications requiring CK410M compliance and integrated support for multiple differential current-mode pairs including CPU, PCIe, and SATA. Verify that the system design accommodates the required external 14.318MHz crystal and precision biasing resistors for the IREF pin. Consider the SMBus interface capabilities if dynamic frequency or spread spectrum adjustment is necessary during operation.

Application Specific Clock/Timing Part Context

The 954226 belongs to the IDT Programmable Timing Control Hub family, specifically optimized for mobile platforms utilizing Intel P4-M architecture. It consolidates multiple clock functions into a single chip, replacing discrete generators. The device supports power management features such as undriven differential pairs for low-power states and PEREQ# pins for selective output control.

Application Specific Clock/Timing Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation. As the product is listed as obsolete, consult the manufacturer's official transition notices or equivalent newer generation timing controllers for direct replacements.

Application Specific Clock/Timing FAQ

What is the maximum CPU output frequency generated by the 954226?

The device generates CPU outputs up to 400MHz when driven by an external 14.318MHz crystal.

How does the 954226 handle power management for differential outputs?

It supports undriven differential CPU and PCI Express pairs in power-down mode and uses PEREQ# pins to selectively enable or disable SATA and PCI Express outputs.

What is the cycle-cycle jitter specification for the PCI Express outputs?

The PCI Express outputs have a cycle-cycle jitter of less than 125ps.