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Product Detailed Parameters
- Description:IC CLOCK GENERATOR 24VFQFPN
- Series:PhiClock™
- Package:Tray
- Mfr:Renesas Electronics Corporation
- PLL:Yes
- Input:HCSL, LVCMOS, LVDS, Crystal
- Output:CML, HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL
- Number of Circuits:1
- Ratio - Input:Output:1:06
- Differential - Input:Output:No/Yes
- Frequency - Max:200MHz, 325MHz
- Divider/Multiplier:Yes/No
- Voltage - Supply:1.71V ~ 1.89V, 2.375V ~ 2.625V, 3.135V ~ 3.465V
- Operating Temperature:-40°C ~ 85°C (TA)
- Mounting Type:Surface Mount
- Package / Case:24-WFQFN Exposed Pad
- Supplier Device Package:24-VFQFPN (4x4)
- Type:Clock Generator
- Grade:-
- Qualification:-
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Overview
The 9FGV1001B000NBGI is a programmable clock generator from Renesas Electronics' PhiClock family, designed for PCIe Gen1 through Gen5 applications. It operates within a supply voltage range of 3.135V to 3.465V and supports output frequencies up to 200MHz. The device features four non-spread-spectrum output copies and two crystal reference input copies, utilizing LP-HCSL signaling with typical RMS phase jitter of 0.267ps at 156.25MHz (12kHz–20MHz). It is housed in a 24-lead VFQFPN package measuring 4.0 x 4.0 x 0.8 mm.
Feature Summary
- PCIe Gen1–Gen5 compliant timing solution
- Four non-spread-spectrum output pairs plus two LVCMOS reference outputs
- Typical RMS phase jitter of 0.267ps at 156.25MHz
- Hardware or I²C selectable configurations via OTP memory
Applications
- PCI Express (PCIe) Gen1 systems
- PCI Express (PCIe) Gen2 systems
- PCI Express (PCIe) Gen3 systems
- PCI Express (PCIe) Gen4 systems
- PCI Express (PCIe) Gen5 systems
Procurement Notes
Verify the specific suffix 'B000' against official Renesas documentation to confirm exact frequency and configuration parameters, as suffixes define factory-programmed settings. Confirm availability status directly with authorized distributors, as stock levels fluctuate. Ensure compliance with RoHS directives and check moisture sensitivity levels prior to PCB assembly.
Selection Notes
Select this component when low jitter performance is critical for PCIe Gen1–Gen5 interfaces. The device supports hardware selection via select pins or software control via I²C, offering flexibility for multi-config designs. Verify that the required output frequency falls within the supported range and that the LP-HCSL output standard matches the downstream receiver requirements.
Part Context
This part belongs to the 9FGV1001 series, which provides multiple integer-related frequency copies. Unlike spread-spectrum variants found in other PhiClock models, this specific configuration delivers fixed-frequency outputs suitable for strict jitter budgets. The device integrates an internal oscillator option and supports various I/O standards including LVDS and LVCMOS depending on the specific sub-model configuration.
Replacement Considerations
Direct replacements within the PhiClock family include the 9FGV1001C series for updated specifications or alternative packaging. Cross-model substitution requires verifying pin compatibility and ensuring the replacement part meets the same PCIe generation jitter requirements. Check datasheet addendums for any changes in electrical characteristics or recommended operating conditions.
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