A3P060-CS121

Field Programmable Gate Array Overview

The A3P060-CS121 is a ProASIC3 Flash Field Programmable Gate Array featuring 60,000 system gates and 96 user I/Os. It utilizes a 130-nm flash-based CMOS process with a core voltage of 1.5 V (range 1.425 V to 1.575 V). The device supports up to 350 MHz system performance and includes 18 kbits of embedded SRAM and 1 kbit of nonvolatile FlashROM. It operates within the commercial temperature range of 0°C to +85°C and is housed in a CS121 Chip Scale Package measuring 6 mm x 6 mm.

Field Programmable Gate Array Feature Summary

• Instant On Level 0 support enables immediate functionality upon power-up without external boot PROMs.
• Integrated AES decryption engine provides secure In-System Programming and IP protection via FlashLock technology.
• Nonvolatile flash architecture retains programmed designs when powered off, eliminating firm errors from high-energy neutrons.

Field Programmable Gate Array Applications

• Secure remote field updates over public networks
• Internet protocol addressing and device serialization
• System calibration settings and asset management

Field Programmable Gate Array Procurement Notes

Verify the specific suffix 'CS121' corresponds to the Chip Scale Package with 0.5 mm pitch. Confirm the absence of an application suffix indicates the Commercial temperature grade (0°C to +85°C). Ensure the ordering code matches the required security license status for AES implementation.

Field Programmable Gate Array Selection Notes

Select this device for applications requiring low pin count and small footprint due to the CS121 package. It is suitable for designs needing Instant On capabilities and moderate logic density. Verify that the 96 available user I/Os meet interface requirements and that the 1.5 V core voltage aligns with system power constraints.

Field Programmable Gate Array Part Context

This component belongs to the Microsemi ProASIC3 Flash family, which offers reprogrammable nonvolatile logic. It bridges the gap between fixed-function ASICs and volatile SRAM-based FPGAs by providing instant-on reliability and lower bill-of-materials costs through the elimination of configuration memory components.

Field Programmable Gate Array Replacement Considerations

Pin-compatible packages across the ProASIC3 family include QN68, VQ100, TQ144, PQ208, FG144, and FG256. Higher density devices such as the A3P125 or A3P250 may serve as upward migration paths if additional logic resources are required.

Field Programmable Gate Array FAQ

Does the A3P060 support ARM Cortex-M1 processors?

No, the standard A3P060 does not support ARM Cortex-M1 processors. Devices supporting this feature begin with the M1A3P prefix.

What is the maximum input frequency for the Clock Conditioning Circuits?

The Clock Conditioning Circuits (CCC) support a wide input frequency range from 1.5 MHz to 350 MHz.

How is the on-chip FlashROM programmed?

The 1 kbit FlashROM is programmed exclusively via the standard IEEE 1532 JTAG programming interface and cannot be programmed from the internal logic array.