A3PE600-PQG208

Overview

The A3PE600-PQG208 is a ProASIC3E flash-based Field Programmable Gate Array manufactured by Microsemi. It features 600,000 system gates and 13,824 VersaTiles (D-flip-flops). The device includes 108 kbits of True Dual-Port SRAM organized into 24 blocks of 4,608 bits each. It supports a maximum system performance frequency of 350 MHz and offers up to 270 user I/Os within an 8-bank architecture. The component utilizes a 130-nm, 7-layer metal process and operates with core voltages supporting 1.5 V-only systems. It is housed in a PQFP-208 package with a 0.50 mm pitch.

Feature Summary

• Nonvolatile flash technology provides Instant On Level 0 support without requiring external boot PROMs.
• Integrated security mechanisms include FlashLock protection and on-chip 128-bit AES decryption for secure ISP.
• Flexible clock conditioning is provided by six Clock Conditioning Circuits (CCCs) with integrated PLLs.
• Advanced I/O structure supports mixed-voltage operation and high-speed standards including LVDS and DDR.

Applications

• Secure remote field updates over public networks
• Consumer electronics requiring low power and instant-on capabilities
• Networking and communications equipment
• Avionics systems

Procurement Notes

Verify the specific ordering suffix to confirm temperature grade and packaging compliance. The 'I' suffix indicates Industrial temperature range, while absence implies Commercial range. Confirm RoHS compliance status via the 'G' suffix if required. Ensure the design flow supports the IEEE 1532 programming standard for this flash-based architecture.

Selection Notes

Select this device for designs requiring nonvolatile configuration and immediate system startup. The PQ208 package limits available CCCs to two PLLs at the center east/west positions, though all six CCC blocks remain usable for delay operations. Verify that the 600k gate density meets logic requirements compared to higher-density ProASIC3E variants.

Part Context

This component belongs to the ProASIC3E family, representing third-generation flash FPGAs from Microsemi. It succeeds the ProASIC PLUS family, offering enhanced performance and density. The A3PE600 serves as the entry-level density option within the PQ208 package lineup, providing a cost-effective solution for moderate complexity logic applications.

Replacement Considerations

A3P600-PQG208I

FAQ

How many PLLs are available in the PQ208 package?

Only two PLLs are available in the PQ208 package, located at the center east and west sides. However, all six CCC blocks can still be utilized for simple clock delay operations.

Does the A3PE600 require an external configuration PROM?

No. As a flash-based FPGA, it stores configuration data on-chip and supports Instant On Level 0, eliminating the need for external boot PROMs or microcontrollers.

What is the maximum input frequency range for the CCC blocks?

The Clock Conditioning Circuits support a wide input frequency range from 1.5 MHz to 350 MHz.