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— IC芯片 | 连接器 | 传感器 | 被动器件 —
The AD1556ASRL is a digital filter and decimator component within the Analog Devices AD1555/AD1556 chipset, designed to form a complete 24-bit sigma-delta analog-to-digital converter. Operating from a single 3.3 V or 5 V supply (VL), it accepts a modulator bitstream input at up to 1.024 MHz via CLKIN. The device provides output word rates ranging from 250 SPS to 16 kSPS, with corresponding passband frequencies from 93.75 Hz to 6 kHz. It features low power dissipation of 6.2 mW typical at 1 kHz output rate and includes standby modes reducing consumption to 70 µW. Packaged in a 44-lead MQFP (S-44A), it supports hardware or software configuration for gain and bandwidth control.
Verify the ordering suffix RL indicates reel packaging when sourcing. Confirm the AS variant meets the –55°C to +85°C industrial temperature range requirement. Ensure the 44-lead MQFP package footprint matches the PCB layout specifications provided in the datasheet pin configuration diagram.
Select the AD1556ASRL to pair with the AD1555 modulator for high dynamic range applications requiring up to 146 dB total system dynamic range. Choose this component when single-supply digital logic compatibility (3.3 V or 5 V) is required alongside the AD1555's dual analog supplies. Verify that the desired output data rate aligns with the specific filter characteristics and group delay specified in Table II.
The AD1556ASRL functions exclusively as the digital companion to the AD1555 sigma-delta modulator. Together, they constitute a complete 24-bit ADC solution optimized for low-frequency, high-resolution measurements. The AD1556 handles the decimation of the 1-bit bitstream into a 24-bit parallel or serial data word, providing the final digital output for system processing.
No direct public substitute part numbers are documented in the source material. System redesign may be required if replacing this component due to the specific interface timing and configuration register architecture defined for the AD1555/AD1556 chipset.
The maximum CLKIN frequency is 1.075 MHz, with a nominal frequency of 1.024 MHz.
The device enters power-down mode when the PWRDN pin is taken high, stopping convolution cycles and the MCLK signal while retaining register data. Power consumption drops to 70 µW in this state.
Stop-band attenuation is –135 dB for all filters except when the output word rate (FO) is 16 kHz, where it is –86 dB.