AD1877JRZ-RL

Overview

The AD1877JRZ-RL is a stereo, 16-bit oversampling analog-to-digital converter (ADC) based on Sigma-Delta technology. It operates from a single 5 V power supply and features two single-ended analog inputs with an internal voltage reference. The device integrates a fourth-order modulator and a three-stage linear-phase decimation filter, achieving a typical dynamic range of 92 dB and signal-to-noise ratio of 90 dB. It accepts input clocks of 256×FS or 384×FS and provides a flexible serial output interface compatible with I2S formats.

Feature Summary

• 16-bit resolution with 92 dB typical dynamic range and 90 dB S/(THD+N)
• Single 5 V supply operation with integrated voltage reference
• Fourth-order sigma-delta modulator with three-stage FIR decimation filter
• Flexible serial output supporting master and slave modes

Applications

• Consumer digital audio receivers
• Digital audio recorders and portable devices
• CD-R, DCC, MD, and DAT systems
• Multimedia and consumer electronic equipment
• Sampling music synthesizers

Procurement Notes

Verify the specific ordering suffix for reel packaging when sourcing the AD1877JRZ-RL variant. Confirm that the component meets RoHS compliance standards as indicated in official documentation. Ensure that ESD precautions are observed during handling due to the sensitivity of the CMOS process. Check for availability through authorized distributors as stock levels may vary.

Selection Notes

Select this component for applications requiring high-fidelity audio conversion with a single 5 V supply. Ensure the system clock can provide 256×FS or 384×FS frequencies relative to the desired sampling rate. Verify that the input signals are AC coupled to allow proper autocalibration of DC offsets. Consider the 28-lead SOIC package constraints for PCB layout and thermal management.

Part Context

The AD1877 is part of Analog Devices' audio ADC portfolio designed for digital audio bandwidth applications. It utilizes a proprietary differential switched-capacitor architecture to minimize idle tones and ensure monotonicity. The device is fabricated using a 0.8 µm CMOS double polysilicon, double metal process, offering robust performance in consumer electronics.

Replacement Considerations

No direct public substitute part numbers are confirmed in the provided documentation. Evaluate alternative ADCs based on pin compatibility, resolution, and supply voltage requirements if replacement is necessary.

FAQ

How does the AD1877 handle DC offset errors?

The AD1877 uses on-chip automatic offset calibration that occurs immediately after reset. This procedure nulls out offsets in the single-to-differential converter, analog modulator, and decimation filter, assuming the inputs are AC coupled.

What is the group delay of the AD1877?

The group delay is determined by the digital decimation filter and is calculated as 36/FS seconds. For common sample rates, this is approximately 750 µs at 48 kHz, 816 µs at 44.1 kHz, and 1125 µs at 32 kHz.

Can the AD1877 operate in both master and slave modes?

Yes, the AD1877 supports both serial port master and slave modes. In master mode, serial interface clocks are internally derived from CLKIN. In slave mode, all clocks must be externally derived from a common source.