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The AD1892JRRL is a digital audio receiver and asynchronous sample rate converter in a 28-lead SOIC package. It operates on a single +5 V supply within an industrial temperature range of –40 °C to +85 °C. The device supports EIAJ CP-340, IEC-958, AES/EBU, and S/PDIF standards with a 1:5 upsampling range and 1:0.85 downsampling range. Key electrical parameters include a 120 dB dynamic range, –113 dB THD+N at 1 kHz, and operational current of 60 mA.
Verify the specific ordering suffix 'RR' indicates reel packaging when sourcing components. Confirm that the part number matches the exact 28-lead SOIC specification required for the target design. Ensure compatibility with the specified +5 V supply voltage and industrial temperature range during component selection.
Select this component for applications requiring integrated digital reception and sample rate conversion without external converters. Verify that the system master clock frequency aligns with the required 512 times output sample rate constraint. Ensure the design accommodates the 28-lead SOIC footprint and provides adequate decoupling capacitors for the digital supply.
This part belongs to the AD1892 family of integrated digital receivers and rate converters manufactured by Analog Devices Inc. It utilizes the company's SamplePort technology for high-performance asynchronous sample rate conversion. The device combines digital audio reception capabilities with robust jitter rejection features suitable for professional and consumer audio interfaces.
The AD1892JR is a compatible alternative offering identical specifications in a standard tube package rather than reel packaging. Both parts share the same functional characteristics, pinout, and performance metrics within the industrial temperature range.
The AD1892 supports EIAJ CP-340 (CP-1201), IEC-958, AES/EBU, and S/PDIF compatible digital audio streams.
The master clock (MCLK) must be synchronous with the output sample rate at exactly 512 times the output sample frequency (512 · FSOUT).
The SYNC input allows multiple AD1892 devices in a system to be phase and group delay synchronized to the same LEFT/RIGHT clock signal.