AD1937WBSTZ-RL

Overview

The AD1937WBSTZ-RL is a high-performance, single-chip audio codec featuring four differential analog-to-digital converters (ADCs) and eight differential digital-to-analog converters (DACs). It utilizes a multibit sigma-delta architecture with a 24-bit resolution and supports sample rates from 8 kHz to 192 kHz. The device operates on a single 3.3 V supply and includes an integrated phase-locked loop (PLL) for clock generation. Key performance metrics include a dynamic range of 107 dB for ADCs and 112 dB for DACs, with a total harmonic distortion plus noise (THD+N) of -96 dB. It features an I²C control port and is housed in a 64-lead LQFP package.

Feature Summary

• Integrates four differential ADC inputs and eight differential DAC outputs within a single chip.
• Includes an internal phase-locked loop (PLL) to generate master clocks from LRCLK or external crystals.
• Supports multiple serial data formats including right-justified, left-justified, I2S, and TDM modes.
• Features software-controllable clickless mute and log volume control with autoramp function.

Applications

• Automotive audio systems
• Home theater systems
• Set-top boxes
• Digital audio effects processors

Procurement Notes

Verify the specific ordering suffix RL indicates reel packaging when sourcing components. Confirm that the device meets AEC-Q100 automotive qualification requirements if intended for vehicle applications. Ensure the design accommodates the 64-lead LQFP footprint and thermal characteristics specified in the datasheet outline dimensions.

Selection Notes

Select this component for designs requiring high channel counts with differential signaling to minimize noise. The integrated PLL simplifies clock distribution by eliminating the need for separate high-frequency oscillators. Verify compatibility with the host microcontroller's I²C interface and ensure the system power supply aligns with the 3.3 V operating voltage specifications.

Part Context

The AD1937 belongs to the Analog Devices AD193X family of high-performance audio codecs. This family shares common architectural features such as the multibit sigma-delta conversion technology and low EMI design principles. Variants within the series may differ in pin count, output configuration (single-ended vs. differential), or specific feature sets like the number of channels.

Replacement Considerations

The AD1939 is a documented similar part within the same product family offering comparable codec functionality.

FAQ

How does the AD1937 handle clock generation?

The device features an on-chip PLL that can derive the master clock from the LR (frame) clock or an external crystal, eliminating the need for a separate high-frequency master clock source.

What is the purpose of the PD/RST pin?

The PD/RST pin resets all control registers to their default settings. It is active low and should be pulled low by an external resistor to guarantee proper startup behavior.

Can the AD1937 operate without I²C programming?

Yes, the device supports a standalone mode where register settings are configured at reset using the serial control pins (ADDR0, SDA, SCL, ADDR1) without requiring active I²C communication.