AD5674RBCPZ-2-RL7

Overview

The AD5674RBCPZ-2-RL7 is a 16-channel, 12-bit buffered voltage output digital-to-analog converter (DAC) from the nanoDAC+ family. It integrates a 2.5 V internal reference with a typical temperature coefficient of 2 ppm/°C and features a user-selectable gain pin for full-scale outputs of 2.5 V or 5 V. The device operates on a single 2.7 V to 5.5 V supply and supports a 50 MHz SPI interface with readback or daisy-chain capabilities. Packaged in a 28-lead, 4 mm × 4 mm LFCSP, it includes power-on reset logic and low-power shutdown modes.

Feature Summary

• 16 channels in a compact 4 mm × 4 mm LFCSP package
• Integrated 2.5 V reference with 2 ppm/°C typical drift
• User-selectable gain of 1 or 2 via GAIN pin
• 50 MHz SPI interface with readback and daisy-chain support

Applications

• Optical transceivers
• Base station power amplifiers
• Process control PLC input/output cards
• Industrial automation systems
• Data acquisition systems

Procurement Notes

Verify the suffix -2-RL7 against official documentation to confirm specific factory packaging quantities and reel specifications. Ensure compatibility with RoHS standards and check moisture sensitivity levels before procurement.

Selection Notes

Select this model for high-density applications requiring 16 independent analog outputs. Verify that the 12-bit resolution and ±1 LSB INL meet system accuracy requirements. Confirm that the 2.7 V to 5.5 V supply range aligns with the target power architecture.

Part Context

This component belongs to the AD5674/AD5674R/AD5679/AD5679R series. The 'R' designation indicates an integrated internal voltage reference, while the '4' denotes 12-bit resolution. The '2' suffix typically specifies the power-up state configuration.

Replacement Considerations

Direct replacements within the same family include AD5674RBCPZ-1 and AD5674BCPZ-1. Verify if the specific power-up state defined by the '-2' suffix matches the application's initialization requirements.

FAQ

What is the maximum serial clock frequency?

The device supports a serial clock (SCLK) frequency up to 50 MHz.

How does the GAIN pin affect the output range?

Tying GAIN to GND sets the span to 0 V to VREF (2.5 V), while tying it to VLOGIC doubles the span to 0 V to 2 × VREF (5 V).

What is the purpose of the RESET pin?

The asynchronous RESET pin updates the input and DAC registers to zero-scale or midscale when activated, ignoring LDAC pulses during the reset state.