AD7730LBRU

Overview

The AD7730LBRU is a 24-bit analog-to-digital converter (ADC) from Analog Devices, designed for weigh scale and pressure measurement applications. It features a sigma-delta architecture with two buffered differential programmable gain inputs and an on-chip 6-bit DAC for offset removal. The device operates on a single +5 V supply and supports input ranges of ±10 mV to ±80 mV. Key specifications include an offset drift of 5 nV/°C, gain drift of 2 ppm/°C, and line frequency rejection exceeding 150 dB. It utilizes a 2.4576 MHz master clock and communicates via a three-wire serial interface compatible with SPI.

Feature Summary

• 24-bit resolution with no missing codes and 230,000 peak-to-peak counts
• Two-channel programmable gain front end with buffered differential inputs
• Low drift characteristics: 5 nV/°C offset drift and 2 ppm/°C gain drift
• Integrated 6-bit DAC for TARE/offset removal and AC excitation control

Applications

• Weigh scales
• Pressure measurement systems

Procurement Notes

Verify the specific B version industrial temperature range (-40°C to +85°C) and the 2.4576 MHz clock requirement distinct from the standard AD7730. Confirm package availability in 24-lead TSSOP or SOIC formats as per the datasheet. Ensure compatibility with external reference voltages between 1 V and 5 V.

Selection Notes

Select the AD7730L variant specifically when a 2.4576 MHz master clock is required, as opposed to the 4.9152 MHz used by the standard AD7730. Consider the CHP bit configuration for chopping mode to minimize low-frequency drift errors in precision measurements. Verify that the application requires the specified bipolar or unipolar input ranges supported by the PGA.

Part Context

The AD7730L is part of the AD7730 family of bridge transducer ADCs. While functionally similar to the AD7730, the 'L' suffix denotes a different master clock specification (2.4576 MHz vs 4.9152 MHz). Both parts share the same pinout and register set but differ in timing parameters and clock generation requirements.

Replacement Considerations

Direct replacement with the standard AD7730 requires adjusting the master clock source from 2.4576 MHz to 4.9152 MHz. No other functional changes are necessary due to identical pinouts and register configurations.