AD7730LBRZ

Overview

The AD7730LBRZ is a bridge transducer analog-to-digital converter featuring a 24-bit Sigma-Delta architecture with no missing codes. It integrates a two-channel programmable gain front end, buffered differential inputs, and an on-chip 6-bit DAC for offset removal. The device operates from a single +5 V supply and supports reference voltages of 1 V to 5 V. Key performance metrics include an offset drift of 5 nV/°C, gain drift of 2 ppm/°C, and integral nonlinearity of 18 ppm of FSR. It utilizes a serial interface compatible with microcontrollers and DSPs.

Feature Summary

• 24-bit resolution with 230,000 peak-to-peak counts
• Two-channel buffered differential programmable gain amplifier (PGA)
• Integrated 6-bit DAC for TARE/offset removal
• Low drift specifications: 5 nV/°C offset, 2 ppm/°C gain

Applications

• Weigh scales
• Pressure measurement

Procurement Notes

Verify the specific ordering suffix against the manufacturer's current documentation to confirm package type and temperature range. Ensure the master clock frequency matches the AD7730L specification of 2.4576 MHz, as this differs from the standard AD7730 variant. Confirm power supply requirements align with the specified AVDD and DVDD ranges.

Selection Notes

Select the AD7730L over the standard AD7730 when a lower master clock frequency of 2.4576 MHz is required for system synchronization. Verify that the application requires the industrial temperature range of -40°C to +85°C. Ensure the design accommodates the single +5 V supply operation and differential reference input configuration.

Part Context

The AD7730L is a variant of the AD7730 family designed specifically for applications requiring a 2.4576 MHz master clock input. While functionally similar to the AD7730, it is distinguished by its clock specification and availability in SOIC and TSSOP packages. It serves as a complete analog front end for high-precision bridge transducer measurements.

Replacement Considerations

The standard AD7730 is a functional substitute but requires a 4.9152 MHz master clock. Verify clock compatibility before substitution. Other ADI ADCs may require significant circuit redesign due to differences in PGA integration and calibration methods.