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Product Detailed Parameters
- Description:IC DAC 16BIT V-OUT 28PLCC
- Series:-
- Mfr:Analog Devices Inc.
- Package:Tube,Tube
- Number of Bits:16
- Number of D/A Converters:1
- Settling Time:9µs
- Output Type:Voltage - Buffered
- Differential Output:No
- Data Interface:Parallel
- Reference Type:External
- Voltage - Supply, Analog:±11.4V ~ 15.75V
- Voltage - Supply, Digital:5V
- INL/DNL (LSB):±16 (Max), ±1 (Max)
- Architecture:String DAC
- Operating Temperature:-40°C ~ 85°C
- Package / Case:28-LCC (J-Lead)
- Supplier Device Package:28-PLCC (11.51x11.51)
- Mounting Type:Surface Mount
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Overview
The AD7846APZ is a 16-bit voltage output digital-to-analog converter (DAC) manufactured by Analog Devices Inc. using the LC2MOS process. It features a segmented architecture ensuring monotonicity over temperature, with an integral linearity error of ±2 LSBs for the A version. The device includes an on-chip output amplifier configurable for unipolar (0 V to +5 V or +10 V) or bipolar (±5 V or ±10 V) ranges via the RIN pin. It operates with analog supplies of ±11.4 V to ±15.75 V and a digital supply of 4.75 V to 5.25 V. Typical power dissipation is 100 mW. The component is housed in a 28-lead plastic DIP package.
Feature Summary
- 16-bit resolution with guaranteed monotonicity over temperature.
- Microprocessor-compatible interface with readback capability for diagnostic routines.
- On-chip output buffer supports unipolar and bipolar output configurations.
- Low power consumption with typical dissipation of 100 mW.
Applications
- Closed-loop control systems requiring high accuracy.
- Automatic Test Equipment (ATE) utilizing register readback.
- Position measurement applications involving LVDTs.
- Multiplying DAC circuits for signal processing.
Procurement Notes
Verify the suffix 'P' indicates the plastic DIP package and 'A' denotes the industrial temperature range (-40°C to +85°C). Confirm that the specific revision matches the required datasheet specifications, as performance parameters such as settling time and linearity are defined under specific supply voltage conditions. Ensure compatibility with existing PCB footprints for the 28-lead PDIP form factor.
Selection Notes
Select the AD7846APZ when 16-bit monotonicity and low power are critical constraints. The 'A' grade offers tighter linearity specifications (±2 LSB INL) compared to the 'K' grade (±4 LSB INL). Consider the internal deglitching feature which holds the output during code transitions, reducing glitch impulse artifacts at the expense of added settling time. Verify that the parallel interface timing requirements align with the host microprocessor capabilities.
Part Context
The AD7846 belongs to the AD7846 series of precision DACs. It utilizes a unique segmented architecture where four MSBs select a segment on a resistor string, which feeds a 12-bit DAC. This design ensures monotonicity without requiring tight matching of all 16 bits, unlike traditional R-2R architectures. The device is part of Analog Devices' legacy LC2MOS product line, offering high reliability for industrial and instrumentation applications.
Replacement Considerations
Direct pin-compatible replacements within the same family include the AD7846KPZ (commercial temperature, ±4 LSB INL) and AD7846BPZ (industrial temperature, ±4 LSB INL). For applications requiring lower power or different interfaces, consider modern successors like the AD5570, though interface differences require schematic redesign.
FAQ
How does the AD7846 ensure 16-bit monotonicity?
It uses a segmented architecture where the four MSBs select a segment on a 16-resistor string, feeding a 12-bit DAC. This prevents nonmonotonicity caused by amplifier offset voltages during segment transitions.
What is the function of the CLR pin?
The CLR pin resets the DAC latch contents. Asserting CLR while R/W is low loads 000…000, and asserting it while R/W is high loads 100…000, allowing the output to be reset to 0 V in both unipolar and bipolar configurations.
Can the AD7846 be used for multiplying operations?
Yes, it is a full multiplying DAC. To achieve four-quadrant multiplication, tie VREF− to 0 V, apply the AC input to VREF+, and tie RIN to VREF+.
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