AD7871JPZ

Overview

The AD7871JPZ is a complete monolithic 14-bit analog-to-digital converter (ADC) fabricated in LC2MOS technology. It integrates a track-and-hold amplifier, successive approximation ADC, and a 3 V buried Zener reference. The device operates from ±5 V power supplies with a typical power dissipation of 50 mW. It supports an input voltage range of ±3 V and achieves a throughput rate of 83 kSPS. Signal-to-noise ratio is specified at 80 dB for the J version at +25°C. Data output formats include parallel 14-bit word, two 8-bit bytes, or serial stream via the 14/8/CLK pin.

Feature Summary

• Integrates a laser-trimmed internal clock oscillator to eliminate external timing components.
• Provides versatile digital interface options including parallel, byte, and serial data formats.
• Features a self-contained architecture with on-chip reference and track-and-hold amplifier.

Applications

• Digital signal processing
• High speed modems
• Speech recognition and synthesis
• Spectrum analysis
• DSP servo control

Procurement Notes

Verify the specific suffix JPZ corresponds to the commercial temperature range (0°C to +70°C) and PLCC-28 package as documented in the Analog Devices ordering guide. Confirm RoHS compliance status through official manufacturer documentation prior to procurement.

Selection Notes

Select the AD7871JPZ when a 14-bit resolution and 83 kSPS throughput are required within a single chip solution. Ensure the system utilizes ±5 V supplies and requires a ±3 V bipolar input range. Consider the available parallel and serial interface modes for microprocessor compatibility.

Part Context

The AD7871 is part of the AD7871/AD7872 family of LC2MOS sampling ADCs. The AD7871 variant specifically offers multiple data output formats, whereas the AD7872 is restricted to serial output only. Both share identical core conversion specifications and internal architectures.

Replacement Considerations

Publicly confirmed substitute part numbers are not provided in the verified source material. Verify cross-compatibility with other 14-bit SAR ADCs based on pinout and electrical specifications if substitution is necessary.

FAQ

How is the internal clock enabled?

The internal laser-trimmed oscillator is enabled by tying the CLK pin (Pin 5) to VSS. An external TTL-compatible clock may be applied if the internal clock is not used.

What determines the data output format?

The 14/8/CLK input (Pin 28) defines the format. A logic high selects 14-bit parallel output. A logic low or -5 V enables byte or serial data formats.

What is the function of the CREF pin?

CREF is the decoupling point for the on-chip reference. A 10 nF capacitor should be connected between this pin and AGND for specified operation.