AD7872JRZ

Overview

The AD7872JRZ is a complete monolithic 14-bit analog-to-digital converter (ADC) manufactured by Analog Devices Inc. It utilizes a successive approximation register architecture and operates from ±5 V power supplies, accepting bipolar input signals within a ±3 V range. The device features an integrated track-and-hold amplifier, a laser-trimmed internal clock, and a 3 V buried Zener reference. It provides a serial digital interface with an 83 kSPS throughput rate and typical power dissipation of 50 mW. The component is housed in a 16-pin SOIC package.

Feature Summary

• Integrated self-contained laser-trimmed internal clock eliminates the need for external timing components.
• Serial data output format designed for direct interfacing with microprocessors and DSPs.
• On-chip temperature-compensated buried Zener reference minimizes external decoupling requirements.

Applications

• Digital signal processing systems
• High-speed modem applications
• Speech recognition and synthesis circuits
• Spectrum analysis equipment

Procurement Notes

Verify the specific ordering suffix against official manufacturer documentation to confirm package type and temperature rating. Confirm that the required serial interface logic matches the device's open-drain outputs and pull-up resistor specifications. Ensure supply voltages align with the specified ±5 V nominal requirement for optimal performance.

Selection Notes

Select this component when a single-channel 14-bit resolution is required with minimal external circuitry. The AD7872 is distinct from the AD7871 as it exclusively supports serial data output formats. Verify that the system timing accommodates the serial clock constraints and bus relinquish times defined in the datasheet.

Part Context

This part belongs to the AD7871/AD7872 family of fast, complete 14-bit sampling ADCs. While the AD7871 offers parallel and byte interfaces, the AD7872 variant is restricted to serial output only. Both devices share identical analog performance characteristics and internal architectures.

Replacement Considerations

Public confirmed substitute: AD7872KRZ.

FAQ

How is the internal clock enabled on the AD7872?

The internal laser-trimmed oscillator is enabled by tying the CLK pin (Pin 3) to VSS. An external TTL-compatible clock may be applied if synchronization with the digital system is required.

What are the requirements for the serial data outputs?

The SCLK, SDATA, and SSTRB pins require external pull-up resistors. Specifically, a 2 kΩ pull-up is recommended for SCLK, while 4.7 kΩ pull-ups are required for SDATA and SSTRB.

How should the internal reference be decoupled?

A 10 nF capacitor must be connected between the CREF pin and AGND. If the REFOUT pin is used externally, it requires additional decoupling with a series resistor and capacitors to remove voltage spikes.