— IC芯片 | 连接器 | 传感器 | 被动器件 —
Product Detailed Parameters
- Description:IC CLKDATA RECOVERY PLL 20SOIC
- Series:-
- PLL:Yes
- Mfr:Analog Devices Inc.
- Main Purpose:DS-3, STS-1
- Input:ECL
- Output:ECL
- Number of Circuits:1
- Ratio - Input:Output:1:02
- Differential - Input:Output:Yes/Yes
- Frequency - Max:51.84MHz
- Voltage - Supply:-4.5V ~ -5.5V
- Operating Temperature:-40°C ~ 85°C
- Mounting Type:Surface Mount
- Package / Case:20-SOIC (0.295", 7.50mm Width)
- Supplier Device Package:20-SOIC
- Grade:-
- Qualification:-
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Overview
The AD800-52BRZRL is a clock and data recovery integrated circuit designed for telecommunications applications. It employs a second-order phase-locked loop architecture to recover the clock signal and retime Non-Return to Zero (NRZ) data without requiring an external voltage-controlled crystal oscillator or preamble sequence. The device supports a nominal center frequency of 51.84 Mbps, corresponding to the STS-1 standard. It operates with ECL-compatible differential inputs and outputs, powered by a single supply ranging from -4.5 V to -5.5 V. The component is housed in a 20-pin plastic SOIC package and functions within an operating temperature range of -40°C to +85°C.
Feature Summary
- Supports 51.84 Mbps STS-1 data rates with NRZ input
- Integrated PLL eliminates need for external VCXO or preamble
- Differential ECL compatible inputs and outputs
- Single supply operation (-4.5 V to -5.5 V)
- User-programmable loop damping via external capacitor
Applications
- Telecommunications systems requiring STS-1 clock recovery
- Data retiming for high-speed digital signals
- Jitter cleaning in optical networking equipment
Procurement Notes
Verify the specific ordering suffix against manufacturer documentation to confirm package type and temperature grade. Confirm that the RL suffix denotes reel packaging if required for automated assembly processes. Ensure compatibility with existing board layouts regarding the 20-SOIC footprint and power supply requirements before procurement.
Selection Notes
Select this component when designing circuits for 51.84 Mbps synchronous optical networking standards. The internal VCO removes the need for external frequency-setting components. Designers must provide an external capacitor on the CF pins to set the loop damping factor, which influences acquisition time and jitter peaking performance.
Part Context
This part belongs to the AD800/AD802 family of clock recovery ICs. While the AD800-45 targets DS-3 rates and the AD802-155 targets STM-1 rates, the AD800-52 variant is specifically optimized for the 51.84 Mbps STS-1 bit rate. All variants share similar architectural features but differ in nominal center frequency and loop bandwidth settings.
Replacement Considerations
Publicly confirmed substitute part numbers are not available in the provided source material.
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