AD805BN

Overview

The AD805BN is a data retiming phase-locked loop (PLL) manufactured by Analog Devices Inc. Designed for telecommunications applications, it performs clock recovery and data retiming on Nonreturn to Zero (NRZ) data streams. The device operates with standard STS-3 or STM-1 data rates of 155.52 Mbps. It requires an external Voltage-Controlled Crystal Oscillator (VCXO) to function. The circuit supports single-supply operation at +5 V or -5.2 V and accepts NRZ data without requiring a preamble. It is packaged in an 8-pin DIP configuration.

Feature Summary

• Performs clock recovery and data retiming on 155.52 Mbps NRZ data
• Complies with CCITT G.958 Type A jitter tolerance specifications
• Eliminates pattern jitter and features fundamentally no jitter peaking
• Acquires lock within 30 bit periods without preamble requirement

Applications

• Clock recovery for STS-3 or STM-1 telecommunications data
• Data retiming in high-speed digital communication systems
• Large factor frequency multiplication when paired with VCXO

Part Context

The AD805 belongs to the AD805 family of data retiming PLLs. It is distinct from the AD805x series of operational amplifiers. The component is specifically engineered for SONET/SDH layer synchronization tasks, relying on external passive components like VCXOs to define the oscillation parameters.

FAQ

What data rate does the AD805 support?

The AD805 is designed for 155.52 Mbps data rates, corresponding to standard STS-3 or STM-1 telecommunications signals.

Does the AD805 require a preamble for data acquisition?

No, the AD805 accepts NRZ data directly without the need for a preamble to initiate clock recovery.

What is the typical acquisition time for the AD805?

The acquisition time is specified as 30 bit periods.