AD807A-155BRZ

Overview

The AD807A-155BRZ is a fiber optic receiver integrating data quantization, signal level detection, clock recovery, and data retiming for 155 Mbps NRZ signals. It meets CCITT G.958 STM-1 Type A and Bellcore OC-3 requirements. The device features a phase-locked loop with a nominal center frequency of 155.52 MHz and an output jitter of 2.0 degrees RMS. It operates on a single +5 V or -5.2 V supply with a maximum power consumption of 170 mW.

Feature Summary

• Integrates quantizer, signal level detect, PLL clock recovery, and data retiming in a single package.
• Acquires frequency and phase lock on random or scrambled data without requiring a preamble sequence.
• Utilizes a patented phase detector to virtually eliminate pattern jitter throughout the circuit.
• Provides adjustable signal level detection threshold with electrical hysteresis to prevent chatter.

Applications

• SONET OC-3 fiber optic receivers
• SDH STM-1 fiber optic receivers
• STM-1 Regenerator Type A implementations
• OC-3 compliant optical communication systems

Procurement Notes

Verify the specific suffix against the manufacturer's ordering guide to confirm packaging options. The BRZ designation indicates a lead-free RoHS-compliant tube package. Confirm that the required damping factor capacitor value aligns with the desired jitter transfer peaking and acquisition time specifications before finalizing procurement.

Selection Notes

Select this component when a highly integrated solution for 155 Mbps NRZ data is required. Ensure the application can accommodate the single-supply voltage range of +5 V or -5.2 V. Consider the external damping capacitor selection carefully, as it directly influences the loop bandwidth, jitter peaking, and acquisition time performance relative to system timing constraints.

Part Context

The AD807 belongs to Analog Devices' family of high-speed fiber optic receivers. It is designed to replace discrete solutions by combining the functions of a quantizer, comparator, and phase-locked loop into one 16-lead SOIC package. This integration reduces board space and simplifies the design of SONET/SDH compliant optical links.

Replacement Considerations

The AD807A-155BRRL7 serves as a reel-packaged alternative within the same functional family. Verify pin compatibility and thermal characteristics when substituting between tube and reel formats to ensure mechanical fit within the existing assembly.

FAQ

Does the AD807 require an external crystal for clock recovery?

No, the device uses a phase-locked loop type clock recovery architecture that does not require an external crystal or SAW filter for frequency acquisition.

How is the jitter peaking of the PLL controlled?

Jitter peaking is controlled by selecting the value of an external damping factor capacitor connected between pins CF1 and CF2. Larger capacitance values generally reduce peaking but increase acquisition time.

What is the purpose of the SDOUT pin?

The SDOUT pin provides a signal detect output that indicates whether the input signal amplitude has fallen below a user-adjustable threshold, signaling a loss of signal condition.