AD808-622BRRL7

Overview

The AD808-622BRRL7 is a fiber optic receiver with quantizer, clock recovery, and data retiming for 622 Mbps NRZ data. It meets CCITT G.958 STM-4 Type A and Bellcore OC-12 requirements. Output jitter is 2.5 degrees RMS. The device features a phase-locked loop type clock recovery without a crystal, accepting data without preamble. Quantizer sensitivity is 4 mV typical, with a level detect range of 10 mV to 40 mV. It operates from a single +5 V or -5.2 V supply, consuming 400 mW.

Feature Summary

• Integrated clock recovery and data retiming for 622 Mbps NRZ signals
• PLL-based frequency acquisition without external crystals or SAW filters
• Programmable signal level detection with electrical hysteresis
• Low output jitter of 2.5 degrees RMS using differential architecture

Applications

• SONET OC-12 fiber optic receivers
• SDH STM-4 regenerator systems
• High-speed optical communication front ends
• Telecommunications infrastructure equipment

Procurement Notes

Verify the specific ordering suffix BRRL7 indicates the 750-piece reel packaging option when sourcing components. Confirm that the temperature range covers the required operational environment of -40°C to +85°C. Ensure compatibility with the 16-lead narrow SOIC package dimensions for board layout. Check for ESD sensitivity precautions during handling and storage as specified in the datasheet warnings.

Selection Notes

Select this component for applications requiring integrated clock recovery and retiming at 622 Mbps without external timing crystals. Consider the 4 mV quantizer sensitivity and 10 mV to 40 mV programmable level detect range for signal conditioning needs. Evaluate the 400 mW power consumption against thermal constraints. Ensure the design can accommodate the external damping capacitor for PLL loop stability and jitter transfer characteristics.

Part Context

The AD808 is part of Analog Devices' high-speed signal processing portfolio, designed specifically for optical communication interfaces. It combines analog quantization with digital clock recovery functions. This integration reduces the component count and board space required for SONET/SDH receiver designs compared to discrete solutions.

Replacement Considerations

Public confirmed substitutes are not available in the provided documentation. Verify functional equivalence regarding jitter tolerance, input sensitivity, and pinout compatibility if considering alternative manufacturers.

FAQ

Does the AD808 require an external crystal for clock recovery?

No, the AD808 uses a phase-locked loop with a frequency acquisition control loop that does not require an external crystal or SAW filter for frequency acquisition.

What is the typical quantizer sensitivity of the AD808?

The typical quantizer sensitivity is 4 mV, allowing the device to correctly interpret low-amplitude input signals.

How is the PLL loop damping configured?

The loop damping is user-programmable via a single external capacitor connected between pins CF1 and CF2. A 0.47 μF capacitor provides a damping ratio of approximately 5 at 622 MHz.