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Product Detailed Parameters
- Description:IC DAC 16BIT A-OUT 56LFCSP
- Series:TxDAC+®
- Mfr:Analog Devices Inc.
- Package:Tape & Reel (TR)
- Number of Bits:16
- Number of D/A Converters:2
- Settling Time:-
- Output Type:Current - Unbuffered
- Differential Output:Yes
- Data Interface:JESD204B
- Reference Type:Internal
- Voltage - Supply, Analog:3.13V ~ 3.47V
- Voltage - Supply, Digital:1.14V ~ 1.26V
- INL/DNL (LSB):±10, ±5
- Architecture:Current Source
- Operating Temperature:-40°C ~ 85°C
- Package / Case:56-WFQFN Exposed Pad, CSP
- Supplier Device Package:56-LFCSP-WQ (8x8)
- Mounting Type:Surface Mount
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Overview
The AD9152BCPZRL is a dual, 16-bit high dynamic range digital-to-analog converter (DAC) from the TxDAC+ family. It supports a maximum sample rate of 2.25 GSPS and features a flexible four-lane JESD204B interface. The device includes an internal reference voltage of 0.5 V, programmable full-scale output current ranging from 4 mA to 20 mA, and a low power architecture consuming 1223 mW at 1.5 GSPS. It operates within a temperature range of -40°C to +85°C and is housed in a 56-lead LFCSP package.
Feature Summary
- Dual-channel 16-bit DAC with a maximum update rate of 2.25 GSPS
- Four-lane JESD204B serial interface supporting up to 12.38 Gbps per lane
- Integrated digital datapath with selectable 1×, 2×, 4×, and 8× interpolation filters
- Programmable transmit enable function for power optimization
Applications
- Wireless communications base stations
- Multicarrier LTE and GSM systems
- Software defined radios
- Wideband repeaters and point-to-point microwave radios
Procurement Notes
Verify the specific suffix RL7 against the official Analog Devices ordering guide to confirm reel packaging specifications. Ensure that the required supply voltages (AVDD33, PVDD12, CVDD12, SVDD12, DVDD12, SIOVDD33, IOVDD) are correctly configured for the target operating conditions before integration.
Selection Notes
Select this component when designing systems requiring high linearity and wide bandwidth up to the Nyquist frequency. Consider the fixed latency characteristics and Subclass 1 JESD204B support if multichip synchronization is required. Verify that the host processor can drive the JESD204B interface speeds up to 12.38 Gbps per lane.
Part Context
This part belongs to the AD9152 series of TxDAC+ converters. It is designed to interface seamlessly with Analog Devices analog quadrature modulators such as the ADRF6720. The device utilizes a proprietary low spurious and distortion design to support single carrier LTE 20 MHz bandwidth applications.
Replacement Considerations
Public confirmed substitute part numbers are not available in the provided documentation.
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