AD9162BBCZ

Overview

The AD9162BBCZ is a 16-bit, high-performance RF digital-to-analog converter (DAC) from Analog Devices. It supports a minimum DAC update rate of 12 GSPS and direct RF synthesis at 6 GSPS. The device features a quad-switch architecture coupled with a 2× interpolator filter, enabling effective update rates up to 12.8 GSPS in specific modes. It offers flexible analog bandwidths: DC to 2.5 GHz in baseband 1× bypass mode, DC to 6 GHz in 2× NRZ mode, and 1.5 GHz to 7.5 GHz in Mix-Mode operation. The output current is programmable from 8 mA to 38.76 mA. Data input is handled via up to eight JESD204B SERDES lanes, configurable for lane speed and count. The component is housed in an 8.0 mm × 8.0 mm, 165-ball CSP_BGA package with a 0.5 mm pitch.

Feature Summary

• 16-bit resolution with a minimum DAC update rate of 12 GSPS and maximum of 12.8 GSPS with FIR85 enabled.
• Supports Direct RF synthesis up to 6 GSPS and Mix-Mode operation reconstructing carriers up to 7.5 GHz.
• Programmable output current ranging from 8 mA to 38.76 mA.
• Up to eight JESD204B SERDES lanes with programmable lane speed and number of lanes.

Applications

• Broadband communications systems
• DOCSIS 3.1 cable modem termination system (CMTS), video on demand (VOD), and edge quadrature amplitude modulation (EQAM)
• Wireless communications infrastructure including W-CDMA, LTE, and LTE-A
• Radar and jammer systems

Procurement Notes

Verify the ordering suffix BBCZ corresponds to the 165-ball, 8.0 mm × 8.0 mm, 0.5 mm pitch CSP_BGA package with leaded ball options as specified in the datasheet. Confirm that the required performance parameters, such as SFDR and power consumption, align with the test conditions listed in the AC and Power Supply specifications tables for the target operating temperature range of -40°C to +85°C.

Selection Notes

Select the AD9162BBCZ when 16-bit resolution is required for high dynamic range applications. Ensure the system design accommodates the 165-ball CSP_BGA footprint. Consider the interpolation factors (2×, 3×, 4×, etc.) and FIR85 filter usage to optimize power dissipation and meet specific Nyquist zone requirements. Verify that the host FPGA or processor can support the necessary JESD204B lane speeds and SYSREF timing constraints.

Part Context

The AD9162 is part of the AD9161/AD9162 family of RF DACs, distinguished by its 16-bit resolution compared to the AD9161's 11-bit resolution. Both share similar architectures and capabilities, but the AD9162 provides higher accuracy and dynamic range. The BBCZ suffix specifically denotes the smaller 165-ball BGA package variant, whereas other suffixes like BBCA denote the larger 169-ball package.

Replacement Considerations

The AD9161 serves as a lower-resolution alternative within the same family. For pin-compatible replacements with different resolutions, verify the package dimensions; the AD9162BBCZ (165-ball, 8x8mm) is not pin-compatible with the AD9162BBCA (169-ball, 11x11mm). No other direct cross-model substitutes are documented in the provided text.