AD9214BRS-80

Overview

The AD9214BRS-80 is a 10-bit monolithic sampling analog-to-digital converter (ADC) operating at a maximum conversion rate of 80 MSPS. It features an on-chip track-and-hold circuit and requires only a single 3.3 V supply (2.7 V to 3.6 V). The device offers a 300 MHz analog bandwidth and supports both 1 V p-p and 2 V p-p differential input ranges via the DFS/GAIN pin. Digital outputs are TTL/CMOS compatible with a separate DrVDD supply for logic interfacing. Power consumption is 285 mW at full speed, reducing to 30 mW in power-down mode.

Feature Summary

• Integrated track-and-hold circuit eliminates external driver components for many applications.
• Single 3.3 V supply operation simplifies system power design.
• Configurable data format and analog input range options via the DFS/GAIN pin.
• Low power consumption with dedicated sleep mode capability.

Applications

• Battery-powered instruments
• Hand-held scopemeters
• Low-cost digital oscilloscopes
• Ultrasound equipment

Procurement Notes

Verify the specific suffix 'R' indicates the reel packaging variant when sourcing this component. Confirm that the ordering code matches the required 80 MSPS performance tier within the AD9214 family. Ensure compatibility with the industrial temperature range specifications during procurement planning.

Selection Notes

Select the AD9214BRS-80 when an 80 MSPS sampling rate is required between the 65 MSPS and 105 MSPS variants. Consider the 1 V p-p or 2 V p-p input range configuration based on the signal source impedance. Evaluate the separate DrVDD supply requirement if interfacing with non-3.3 V logic families.

Part Context

This component belongs to the AD9214 series of high-speed, low-power ADCs from Analog Devices. The series includes variants optimized for 65 MSPS, 80 MSPS, and 105 MSPS conversion rates. All variants share the same 28-lead SSOP package and architectural features, differing primarily in their maximum clock frequency specifications.

Replacement Considerations

Direct replacements include the AD9214BRS-65 and AD9214BRS-105. Verify that the system timing constraints accommodate the slightly different maximum conversion rates of these substitutes without requiring redesign of the encode clock distribution network.

FAQ

How is the analog input voltage range configured?

The DFS/GAIN pin determines the range. Connecting it to AGND or AVDD sets a 1 V p-p range, while connecting it to REF or leaving it floating sets a 2 V p-p range.

What is the function of the REFSENSE pin?

REFSENSE selects the reference mode. Connecting it to AGND enables the internal 1.25 V reference, whereas connecting it to AVDD disables the internal reference for external drive.

Can the AD9214 operate with AC-coupled inputs?

Yes, both the analog inputs and the ENCODE clock input are internally biased, allowing for AC coupling of the signal sources.