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Product Detailed Parameters
- Description:IC ADC 12BIT PIPELINED 64LFCSP
- Series:-
- Mfr:Analog Devices Inc.
- Package:Bulk,Tray
- Number of Bits:12
- Sampling Rate (Per Second):80M
- Number of Inputs:2
- Input Type:Differential, Single Ended
- Data Interface:Parallel
- Configuration:S/H-ADC
- Ratio - S/H:ADC:1:01
- Number of A/D Converters:2
- Architecture:Pipelined
- Reference Type:Internal
- Voltage - Supply, Analog:1.7V ~ 1.9V
- Voltage - Supply, Digital:1.7V ~ 3.6V
- Features:Simultaneous Sampling
- Operating Temperature:-40°C ~ 85°C
- Package / Case:64-VFQFN Exposed Pad, CSP
- Supplier Device Package:64-LFCSP-VQ (9x9)
- Mounting Type:Surface Mount
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Overview
The AD9231BCPZ-80 is a dual-channel, 12-bit analog-to-digital converter (ADC) from Analog Devices Inc., operating at a maximum sampling rate of 80 MSPS. It utilizes a multistage differential pipeline architecture with output error correction logic to ensure no missing codes across the full operating temperature range. The device features a high-performance sample-and-hold circuit and an on-chip voltage reference. It operates from a single 1.8 V analog supply and supports digital output driver supplies ranging from 1.8 V to 3.3 V. Key performance metrics include a Signal-to-Noise Ratio (SNR) of 71.3 dBFS at a 9.7 MHz input frequency and 69.0 dBFS at 200 MHz. Spurious-Free Dynamic Range (SFDR) reaches 93 dBc at 9.7 MHz and 83 dBc at 200 MHz. Power consumption is specified at 166.5 mW with a 3.3 V digital supply at maximum sampling rates.
Feature Summary
- Multistage differential pipeline architecture with output error correction logic for guaranteed linearity.
- Integrated sample-and-hold circuit and internal voltage reference for simplified system design.
- Flexible digital interface supporting offset binary, gray code, or twos complement data formats.
- Programmable clock divider and duty cycle stabilizer for optimized timing and jitter performance.
Applications
- Diversity radio systems
- Multimode digital receivers
- I/Q demodulation systems
- Smart antenna systems
Procurement Notes
Verify the specific ordering suffix against the manufacturer's current datasheet revision to confirm the 80 MSPS speed grade. Ensure the package type matches the required 64-lead LFCSP footprint. Confirm RoHS compliance status and lead-free specifications prior to procurement. Cross-reference the part number with official distributor catalogs to validate availability and authenticity.
Selection Notes
Select this component when a dual-channel, 12-bit resolution ADC is required for applications demanding up to 80 MSPS throughput. Consider the 1.8 V analog supply requirement and the flexibility of the 1.8 V to 3.3 V digital interface. Evaluate power consumption constraints, noting that higher digital supply voltages increase total power dissipation. Verify compatibility with existing clocking infrastructure due to the integrated divider and stabilizer features.
Part Context
The AD9231BCPZ-80 belongs to the AD9231 family of dual-channel, 12-bit ADCs offered by Analog Devices. This family includes variants with different maximum sampling rates, such as 20 MSPS, 40 MSPS, and 65 MSPS, all sharing the same pinout and architectural foundation. The device is designed for easy migration between different speed grades within the same package, facilitating flexible design iterations without layout changes.
Replacement Considerations
The AD9231BCPZ-80 is pin-compatible with other members of the AD9231 family, including the AD9231BCPZ-20, AD9231BCPZ-40, and AD9231BCPZ-65. Designers can substitute these parts if lower sampling rates are acceptable, provided the electrical characteristics meet the application requirements. No PCB layout modifications are necessary for these replacements due to identical pin configurations.
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